LUDLUM 2360, User Manual

Page: 45 / 72

Model 2360 Technical Manual
Section 8
Ludlum Measurements, Inc. Page 8-3 July 2016
Meter Drive
Pulses are coupled from the µP board to the gate of Q302. Q302 inverts the
pulses at CR403, and C401 provides integration. Integrated meter drive
voltage is coupled from P1-13 via the battery (
BAT
) and
HV
test switch to pin
5 of U311. The meter is driven by the emitter of Q111, coupled as a voltage
follower in conjunction with pin 6 and 7 of U311. R406, “Meter Cal,” is
adjusted to calibrate the ratemeter reading corresponding to the incoming
count rate. R407 and R408 provide temperature compensation for changes
in the meter resistance due to temperature variations.
Refer to Processor Board Drawing 390 × 173 for the following:
Power supply
Battery voltage is coupled to switching regulator U321 and associated
components to p5 V to power the µP and display drivers U211,
212. R101, C101, Q101, and Q201 form a delay switch, which allows U321
to stabilize before the load current is connected to the +5 V supply.
Microprocessor (µP)
U111, Intel N87C51FC, controls all of the data, control inputs, and display
information. The clock frequency is crystal controlled by Y111 and related
components at 6.144 MHz. The µP incorporates internal memory (ROM)
storing the program information. C211 resets the µP at power-up to initiate
the start of the program routine. During the program loop the µP looks at all
of the input switches for initiation or status changes and responds
accordingly.
The µP uses pulse-width modulation to control the analog ratemeter. The
analog output,
RATE
(P1-3) is divided into 255 increments in a 166 µs period.
At full meter deflection the low pulse period – leading edge to leading edge –
will be 166 µs, 500 cpm = 163 µs, 400 cpm = 130 µs, 200 cpm = 65 µs, 100
cpm = 33 µs, and 0 = no pulse or +5 V. The pulses are inverted by Q302 on
the amp/power supply board and then integrated by R403, C401.
LCD Drive
U101 and U001 make up the liquid crystal display drive circuitry. The display
information is sent from the µP to U101 and U001 via
DATA
0-1 lines. Each
bit is latched into the drivers when the
CLOCK
line is brought high, then low
by the µP. When 32 bits have been clocked to the drivers, the