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3-4 Chipset Features Setup
Bank 0/1(2/3, 4/5) DRAM Timing
This will determine the timing of SDRAM. The user can separately adjust the
timing of bank 0/1, 2/3, 4/5.
: SDRAM 10ns (default)—10
–9
nano second
: SDRAM 8ns, normal, medium, fast, turbo
SDRAM Cycle Length: control the DRAM page missing and row miss leadoff
timing.
:2
:3 (default)
DRAM Clock
:Host CLK (default)
System shows the actual DRAM speed the system uses.
:HCLK-33M
:HCLK+33M
Please check DRAM clock for optimize selection.
