4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
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10.5.5
Interrupt routing mode selection register
Offset:
0x58
Reset value:
0x00000000
name:
Interrupt routing mode selection register
Table 10-15 Interrupt Route Selection Register
Bit field
Bit field name
Bit width reset value Visit description
9: 8
ht_int_stripe
2
0x0
R / W corresponds to
3 interrupt routing methods, see 0 interrupt direction for details
Volume register
0x0: ht_int_stripe_1
0x1: ht_int_stripe_2
0x2: ht_int_stripe_4
10.5.6
Receive buffer initial register
Offset:
0x5c
Reset value:
0x07778888
name:
Receive buffer initialization configuration register
Table 10- 16 Receive buffer initial register
Bit field
Bit field name
Bit width reset value Visit description
27:24
rx_buffer_r_data
4
0x0
R / W Receive buffer read data buffer initialization information
23:20
rx_buffer_npc_data 4
0x0
R / W receive buffer npc data buffer initialization information
Page 76
Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
19:16
rx_buffer_pc_data
4
0x0
R / W receive buffer pc data buffer initialization information
15:12
rx_buffer_b_cmd
4
0x0
R / W receive buffer initialization command buffer initialization information
11: 8
rx_buffer_r_cmd
4
0x0
R / W receive buffer read command initialization information
7: 4
rx_buffer_npc_cmd 4
0x0
R / W receive buffer npc command buffer initialization information
3: 0
rx_buffer_pc_cmd
4
0x0
R / W receive buffer pc command buffer initialization information
10.5.7
Receive address window configuration register
The address window hit formula in the HT controller is as follows:
hit = (BASE & MASK) == (ADDR & MASK)
addr_out = TRANS_EN? TRANS | ADDR & ~ MASK: ADDR
It should be noted that when configuring the address window register, the high bit of MASK should be all 1, and the low bit should be all 0. 0 in MASK
The actual number of bits indicates the size of the address window.
The address in the receive address window is the address received on the HT bus. The HT address falling within the P2P window will be regarded as P2P
The command is forwarded back to the HT bus, and the HT address that falls within the normal receive window and is not in the P2P window will be sent to the CPU.
The command at its address will be forwarded back to the HT bus as a P2P command.
Offset:
0x60
Reset value:
0x00000000
name:
HT bus receive address window 0 enable (external access)
Table 10- 17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition
Bit field
Bit field name
Bit width reset value Visit description
31
ht_rx_image0_en
1
0x0
R / W HT bus receives address window 0, enable signal