It is possible to completely bypass the PLL chip to generate the traffic generator clock. It is
therefore possible to proceed with direct injection of clock signals. This is especially interesting
when jitter sensitivity tests of frequency variation tests must be performed.
The external input clock can have an arbitrary value. The frequency is measured and the PLLs are
configured to generate the desired target frequencies. However, it is always better to use common
frequencies for audio and communication system. The unit software will compare the measured
frequencies with known values and take the known values that are close (+/- 0.8%) to the
measured frequency. This is done to reduce the risk of wrongly set target frequencies. If nothing
matches, the PLL parameters will be computed with the measured input frequency value.
When using the PLL, the lowest usable input frequency is 1 MHz.
Note:
When using direct feed, the external clock frequency
must be twice
the desired SoundWire
bus clock (SoundWire clock = 1/2 external clock).
The output clock is fed by one of the two PLL outputs. The Auxiliary clock frequency is manually
programmable.
1.3.4.
Monitoring Signals connector
The monitoring signals are available on a boxed IDC 10 pin header connector with a regular pitch
of 2.54 mm (0.1”). The bottom pins are all connected to ground.
The buffered SoundWire clock signal is a copy of the captured SoundWire clock. It enables scope
probing without disturbing the bus. The buffered SoundWire data signal is a copy of one of the 7
SoundWire data lines. The selected line is control through a script command or directly via the PC
application.
The Data Diff signal is high every time there is a difference between the transmitted data and the
captured data. It indicates where the DUT is writing or if there is a bus clash condition.
The TRIG 1 and TRIG 2 outputs are used to flag specific events happening on the bus. The Trig
Out signals are controlled directly by a script command (to spot a specific part of the script) or by
an internal event decoder that flags specific events (especially in sniffer mode). The event filter
engine is controlled via the PC application.
The monitoring signals use the same signaling level as the GPI/PDM connector.
Pin
Signal
Direction
1
Buffered SW clock
Out
3
Buffered SW data
Out
5
DATA DIFF
Out
7
TRIG 1 OUT
Out
9
TRIG 2 OUT
Out
2..10
Ground
SoundWire Protocol Analyzer
User Manual V1.0
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