TME-ITX-GM45-R1V1
Rev 1.1
Page 11 of 31
LVDS
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical
standard only defining driver output characteristics and receiver input characteristics.
Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a
throughput of up to 784 Mbps on each data output and up to 112 MP/s on the input. When using
both channels, each carry a portion of the data, thus doubling the throughput to a maximum
theoretical pixel rate of 224 MP/s.
There are two LVDS transmitter channels (Channel A and Channel B) in the LVDS interface. Channel
A and Channel B consist of 4-data pairs and a clock pair each.
The LVDS data pair is used to transfer pixel data as well as the LCD timing control signals.
There is a connector supplying the LC-Display's inverter.
LVDS Connector
Connector type: DF14-30P-1.25H (Hirose) (X27)
Pin
Signal
1
VDD (3.3 V, opt.5 V)
2
VDD (3.3 V, opt.5 V)
3
GND
4
GND
5
TXA3 -
6
TXA3 +
7
TXACLK -
8
9
GND
10
TXA2 -
11
TXA2 +
12
TXA1 -
13
TXA1 +
14
TXA0 -
15
TXA0 +
16
GND
17
TXB3 -
18
TXB3 +
19
TXBCLK -
20
21
GND
22
TXB2 -
23
TXB2 +
24
TXB1 -
25
TXB1 +
26
TXB0 -
27
TXB0 +
28
GND
29
LVDS DDC-CLK
30
LVDS DDC-DATA
"A" and "B" in the sign al names denote
the two possible LVDS channels.
X
2
7
