LTC4000
16
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Input Ideal Diode PMOS Selection
The input external PMOS is selected based on the expected
maximum current, power dissipation and reverse volt-
age drop. The PMOS must be able to withstand a gate to
source voltage greater than V
IGATE(ON)
(15V maximum) or
the maximum regulated voltage at the IID pin, whichever
is less. A few appropriate external PMOS for a number of
different requirements are shown at Table 1.
Table 1. PMOS
PART NUMBER
R
DS(ON)
AT
V
GS
= 10V
(Ω)
MAX ID
(A)
MAX VDS
(V)
MANUFACTURER
SiA923EDJ
0.054
4.5
–20
Vishay
Si9407BDY
0.120
4.7
–60
Vishay
Si4401BDY
0.014
10.5
–40
Vishay
Si4435DDY
0.024
11.4
–30
Vishay
SUD19P06-60
0.060
18.3
–60
Vishay
Si7135DP
0.004
60
–30
Vishay
Note that in general the larger the capacitance seen on
the IGATE pin, the slower the response of the ideal diode
driver. The fast turn off and turn on current is limited to
–0.5mA and 0.7mA typical respectively (I
IGATE(FASTOFF)
and
I
IGATE(FASTON)
). If the driver can not react fast enough to a
sudden increase in load current, most of the extra current
is delivered through the body diode of the external PMOS.
This increases the power dissipation momentarily. It is
important to ensure that the PMOS is able to withstand
this momentary increase in power dissipation.
The operation section also mentioned that an external 10M
pull-up resistor is recommended between the IGATE pin
and the CSP pin when the IN pin voltage is expected to
be out of its operating range, at the same time that the
external input ideal diode PMOS is expected to be com-
pletely turned off. Note that this additional pull-up resistor
increases the forward voltage regulation of the ideal diode
function (V
IID,CSP
) from the typical value of 8mV.
The increase in this forward voltage is calculated according
to the following formula:
∆V
IID,CSP REG
= V
GSON
• 20k/R
IGATE
where V
GSON
is the source to gate voltage required to
achieve the desired ON resistance of the external PMOS
and R
IGATE
is the external pull-up resistor from the IGATE
applicaTions inForMaTion
pin to the CSP pin. Therefore, for a 10M R
IGATE
resistor
and assuming a 10V V
GSON
, the additional forward voltage
regulation is ∆V
IID,CSP REG
= 20mV, and the total forward
voltage regulation is 28mV (typ). It is recommended to
set the R
IGATE
such that this additional forward voltage
regulation value does not exceed 40mV.
Input Current Limit Setting and Monitoring
The regulated input current limit is set using a resistor at
the IL pin according to the following formula:
R
IS
=
V
IL
20 • I
ILIM
where V
IL
is the voltage on the IL pin. The IL pin is internally
pulled up with an accurate current source of 50µA. Therefore
an equivalent formula to obtain the input current limit is:
R
IL
=
I
LIM
• R
IS
2.5µA
⇒
I
ILIM
=
R
IL
R
IS
• 2.5µA
The input current through the sense resistor is available
for monitoring through the IIMON pin. The voltage on
the IIMON pin varies with the current through the sense
resistor as follows:
V
IIMON
=
20 • I
RIS
• R
IS
=
20 • V
IN
– V
CLN
(
)
The regulation voltage level at the IIMON pin is clamped
at 1V with an accurate internal reference. At 1V on the
IIMON pin, the input current limit is regulated at the fol-
lowing value:
I
ILIM(MAX)
(A)
=
0.050V
R
IS
(
Ω
)
When this maximum current limit is desired, leave the IL
pin open or set it to a voltage >1.05V such that amplifier
A4 can regulate the IIMON voltage accurately to the internal
reference of 1V.
If the input current is noisy, add a filter capacitor to the CLN
pin to reduce the AC content. For example, when using a
buck DC/DC converter, the use of a C
CLN
capacitor is strongly
recommended. Where the highest accuracy is important, pick
the value of C
CLN
such that the AC content is less than or
equal to 50% of the average voltage across the sense resistor.