LTC3810-5
9
38105fd
pin FuncTions
V
ON
(Pin 2): On-Time Voltage Input. Voltage trip point
for the on-time comparator. Tying this pin to the output
voltage or to an external resistive divider from the output
makes the on-time proportional to V
OUT
. The comparator
defaults to 0.7V when the pin is grounded and defaults to
2.4V when the pin is connected to INTV
CC
. Tie this pin to
INTV
CC
in high V
OUT
applications to use a lower R
ON
value.
V
RNG
(Pin 3): Sense Voltage Limit Set. The voltage at this
pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive di-
vider from INTV
CC
. The nominal sense voltage defaults to
95mV when this pin is tied to ground, and 215mV when
tied to INTV
CC
.
PGOOD (Pin 4): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between ±10% of the regulation point. The output
voltage must be out of regulation for at least 120µs before
the power good output is pulled to ground.
MODE/SYNC (Pin 5): Pulse Skip Mode Enable/Sync Pin.
This multifunction pin provides pulse skip mode enable/
disable control and an external clock input to the phase
detector. Pulling this pin below 0.8V or to an external
logic-level synchronization signal disables pulse skip mode
operation and forces continuous operation. Pulling this
pin above 0.8V enables pulse skip mode operation. For a
clock input, the phase-locked loop will force the rising top
gate signal to be synchronized with the rising edge of the
clock signal.This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor
to regulate a second output voltage.
I
TH
(Pin 6): Error Amplifier Compensation Point and Cur-
rent Control Threshold. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.6V with 1.2V corresponding to zero sense
voltage (zero current).
V
FB
(Pin 7): Feedback Input. Connect V
FB
through a resistor
divider network to V
OUT
to set the output voltage.
PLL/LPF (Pin 8): The phase-locked loop’s lowpass filter
is tied to this pin. The voltage at this pin defaults to 1.2V
when the IC is not synchronized with an external clock at
the MODE/SYNC pin.
SS/TRACK (Pin 9): Soft-Start/Tracking Input. For soft-start,
a capacitor to ground at this pin sets the ramp rate of the
output voltage (approximately 0.6s/µF). For coincident or
ratiometric tracking, connect this pin to a resistive divider
between the voltage to be tracked and ground.
SHDN
(Pin 12): Shutdown Pin. Pulling this pin below
1.5V will shut down the LTC3810-5, turn off both of the
external MOSFET switches and reduce the quiescent sup-
ply current to 240µA.
UVIN (Pin 13): UVLO Input. This pin is input to the internal
UVLO and is compared to an internal 0.8V reference. An
external resistor divider is connected to this pin and the
input supply to program the undervoltage lockout voltage.
When UVIN is less than 0.8V, the LTC3810-5 is shut down.
NDRV (Pin 14): Drive Output for External Pass Device of
the Linear Regulator for INTV
CC
. Connect to the gate of
an external NMOS pass device and a pull-up resistor to
the input voltage V
IN
.
EXTV
CC
(Pin 15): External Driver Supply Voltage. When
this voltage exceeds 4.7V, an internal switch connects this
pin to INTV
CC
through an LDO and turns off the exter nal
MOSFET connected to NDRV, so that controller and gate
drive are drawn from EXTV
CC
.
INTV
CC
(Pin 16): Main Supply Pin. All internal circuits ex-
cept the output drivers are powered from this pin. INTV
CC
should be bypassed to ground (Pin 10) with at least a 0.1µF
capacitor in close proximity to the LTC3810-5.
DRV
CC
(Pin 17): Driver Supply Pin. DRV
CC
supplies power
to the BG output driver. This pin is normally connected to
INTV
CC
. DRV
CC
should be bypassed to BGRTN (Pin 20)
with a low ESR (X5R or better) 1µF-10µF capacitor in close
proximity to the LTC3810-5.
