Linear Technology LTC3810-5 Datasheet Download Page 30

LTC3810-5

30

38105fd

If the external frequency (f

MODE

) is greater than the 

oscillator frequency f

O

, current is sourced continuously, 

pulling up the PLL/LPF pin. When the external frequency 

is less than f

O

, current is sunk continuously, pulling down 

the PLL/LPF pin. If the external and internal frequencies 

are the same but exhibit a phase difference, the current 

sources turn on for an amount of time corresponding to 

the phase difference. Thus the voltage on the PLL/LPF  

pin is adjusted until the phase and frequency of the external 

and internal oscillators are identical. At this stable operating 

point the phase comparator output is open and the filter 

capacitor C

LP

 holds the voltage. The LTC3810-5 MODE/

SYNC pin must be driven from a low impedance source 

such as a logic gate located close to the pin.
The loop filter components (C

LP

, R

LP

) smooth out the 

current pulses from the phase detector and provide a 

stable input to the voltage controlled oscillator. The filter 

components C

LP

 and R

LP

 determine how fast the loop 

acquires lock. Typically R

LP 

= 10kΩ and C

LP

 is 0.01µF 

to 0.1µF.

Efficiency Considerations
The percent efficiency of a switching regulator is equal to 

the output power divided by the input power times 100%. 

It is often useful to analyze individual losses to determine 

what is limiting the efficiency and which change would 

produce the most improvement. Although all dissipative 

elements in the circuit produce losses, four main sources 

account for most of the losses in LTC3810-5 circuits:
1. DC I

2

R losses. These arise from the resistances of the 

MOSFETs, inductor and PC board traces and cause the 

efficiency to drop at high output currents. In continuous 

mode the average output current flows through L, but is 

chopped between the top and bottom MOSFETs. If the 

two MOSFETs have approximately the same R

DS(ON)

then the resistance of one MOSFET can simply be 

summed with the resistances of L and the board traces 

to obtain the DC I

2

R loss. For example, if R

DS(ON)

 = 

0.01Ω and R

L

 = 0.005Ω, the loss will range from 15mW 

to 1.5W as the output current varies from 1A to 10A.

2. Transition loss. This loss arises from the brief amount 

of time the top MOSFET spends in the saturated region 

during switch node transitions. It depends upon the 

input voltage, load current, driver strength and MOSFET 

capacitance, among other factors. The loss is signifi-

cant at input voltages above 20V and can be estimated 

from the second term of the P

MAIN

 equation found in 

the Power MOSFET Selection section. When transition 

losses are significant, efficiency can be improved by 

lowering the frequency and/or using a top MOSFET(s) 

with lower C

RSS

 at the expense of higher R

DS(ON)

3. INTV

CC

/DRV

CC

 current. This is the sum of the MOSFET 

driver and control currents. Control current is typically 

about 3mA and driver current can be calculated by:  

I

GATE

 = f(Q

G(TOP)

 + Q

G(BOT)

), where Q

G(TOP)

 and Q

G(BOT)

 

are the gate charges of the top and bottom MOSFETs. 

This loss is proportional to the supply voltage that 

INTV

CC

/DRV

CC

 is derived from, i.e., V

IN

 for the external 

NMOS linear regulator, V

OUT

 for the internal EXTV

CC

 

regulator, or V

EXT

 when an external supply is connected 

to INTV

CC

/DRV

CC

.

4. C

IN

 loss. The input capacitor has the difficult job of fil- 

tering the large RMS input current to the regulator. It  

must have a very low ESR to minimize the AC I

2

R loss  

and sufficient capacitance to prevent the RMS current  

from  causing additional upstream losses in fuses or 

batteries. 

Other losses, including C

OUT

 ESR loss, Schottky diode D1 

conduction loss during dead time and inductor core loss 

generally account for less than 2% additional loss. When 

making adjustments to improve efficiency, the input cur-

rent is the best indicator of changes in efficiency. If you 

make a change and the input current decreases, then the 

efficiency has increased. If there is no change in input 

current, then there is no change in efficiency.

Checking Transient Response
The regulator loop response can be checked by look-

ing at the load transient response. Switching regulators 

take several cycles to respond to a step in load current.  

applicaTions inForMaTion

Summary of Contents for LTC3810-5

Page 1: ...ase Station Power Supplies n Networking Equipment Servers n Automotive and Industrial Control Systems n High Voltage Operation Up to 60V n Large 1 Gate Drivers n No Current Sense Resistor Required n D...

Page 2: ...ODE SYNC ITH VFB PLL LPF SENSE NC NC NC SENSE BGRTN BG DRVCC NC I ON NC NC NC BOOST TG SW SS TRACK NC NC SHDN UVIN NDRV EXTV CC INTV CC TJMAX 125 C JA 34 C W EXPOSED PAD PIN 33 IS SGND MUST BE SOLDERE...

Page 3: ...2 V ISHDN SHDN Pin Input Current 0 1 A VUVIN UVIN Undervoltage Lockout UVIN Rising UVIN Falling Hysteresis l l 0 86 0 78 0 07 0 89 0 80 0 10 0 92 0 82 0 12 V V V VVCCUV INTVCC Undervoltage Lockout Lin...

Page 4: ...EXTVCC 6V VEXTVCC 15V 5 2 5 5 5 8 V DVEXTVCC 1 VEXTVCC VINTVCC at Dropout ICC 20mA VEXTVCC 5V 75 150 mV DVLOADREG 1 INTVCC Load Regulation from EXTVCC ICC 0mA to 20mA VEXTVCC 10V 0 01 VINTVCC 2 INTVCC...

Page 5: ...RT 0 1 FRONT PAGE CIRCUIT 200 s DIV VOUT 5V DIV VFB 0 5V DIV IL 5A DIV 38105 G04 VIN 48V FRONT PAGE CIRCUIT 500 s DIV 38105 G05 VOUT 5V DIV SS TRACK 0 5V DIV VFB 0 5V DIV IL 5A DIV VIN 48V ILOAD 1A MO...

Page 6: ...300 400 3 0 VRNG 2V 1 4V 1V 0 7V 0 5V ION CURRENT A 10 10 ON TIME ns 100 1000 10000 100 1000 10000 38105 G12 VON INTVCC VON VOLTAGE V 0 400 500 700 1 5 2 5 38105 G13 300 200 0 5 1 2 3 100 0 600 ON TI...

Page 7: ...VINTVCC 5V 50 25 75 25 0 50 100 150 125 TEMPERATURE C R DS ON 1 25 1 50 1 75 38105 G20 1 00 0 75 0 50 0 25 VBOOST VINTVCC 5V DRVCC BOOST VOLTAGE V 4 5 7 9 11 13 PEAK SOURCE CURRENT A 3 0 2 5 2 0 1 5 1...

Page 8: ...stics INTVCC VOLTAGE V 0 200 250 300 6 10 38105 G27 150 100 2 4 8 12 14 50 0 INTV CC CURRENT A 50 25 75 25 0 50 100 150 125 TEMPERATURE C SS TRACK CURRENT A 2 3 38105 G28 1 0 LOAD CURRENT A 0 2 0 3 0...

Page 9: ...tage ranges from 0V to 2 6V with 1 2V corresponding to zero sense voltage zero current VFB Pin7 FeedbackInput ConnectVFBthrougharesistor divider network to VOUT to set the output voltage PLL LPF Pin 8...

Page 10: ...resistor or MOSFET SW Pin 25 Switch Node Connection to Inductor and Bootstrap Capacitor The voltage swing at this pin is 0 7V a Schottky diode external voltage drop to VIN TG Pin 26 Top Gate Drive Th...

Page 11: ...24 SW 25 TG BOOST CB 26 27 EXTVCC 15 INTVCC NDRV 16 14 UV 0 72V OV 0 88V CVCC VOUT M2 M1 M3 L1 COUT CIN SS TRACK DB 4 VIN VIN SENSE 20 OVERTEMP SENSE FOLDBACK 0 8V REF 5V REG INTVCC ITH 5 8 ION 31 VI...

Page 12: ...behaves as a constant frequency part against the load and supply variations Pulling the SHDN pin low forces the controller into its shutdown state turning off both M1 and M2 Forcing a voltage above 1...

Page 13: ...w side driver drives the bottom side MOSFET see Figure 3 The bottom side driver is supplied directly from the DRVCC pin The top MOSFET drivers are biased from floating bootstrap capacitor CB which nor...

Page 14: ...OSFETissizedforproperdissipationand thedrivershutdown restartforVOUT 4 7Visdisabled This scheme is less efficient but may be necessary if VOUT 4 7V and a boost network is not desired 3 Tricklechargemo...

Page 15: ...e tied to SGND or INTVCC in which case the nominal sense voltage defaults to 95mV or 215mV respectively Connecting the SENSE and SENSE Pins The LTC3810 5 can be used with or without a sense re sistor...

Page 16: ...LLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above BothMOSFETshaveI2RlosseswhilethetopsideN channel equation incudes an additio...

Page 17: ...ration as the input supply varies f VOUT VVON RON 76pF HZ Toholdfrequencyconstantduringoutputvoltagechanges tie the VON pin to VOUT or to a resistive divider from VOUT when VOUT 2 4V The VON pin has i...

Page 18: ...t occurs at the highest VIN To guarantee that ripple current does not exceed a specified maximum the inductance should be chosen according to L VOUT f IL MAX 1 VOUT VIN MAX Once the value for L is kno...

Page 19: ...higher ESR and lower RMS current ratings A good approach is to use a combination of aluminum electrolyticsforbulkcapacitanceandceramicsforlowESR and RMS current If the RMS current cannot be handled by...

Page 20: ...connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET This capacitor is charged through diode DB from DRVCCwhentheswitchnodeislow WhenthetopMOSFET turns on the switch node...

Page 21: ...tart cycles are then attempted at low duty cycle intervals to try to bring the output back up see Figure 10 This fault timeout operation is enabled by choosing the choosing RNDRV such that the resisto...

Page 22: ...t up Once the INTVCC DRVCC voltage reaches the trickle charge UV threshold of 9V the drivers will turn on andstartdischargingCINTVCC CDRVCC ataratedetermined by the driver current IG In order to ensur...

Page 23: ...he modulator the output filter and load and the feedback amplifier with its compensation network All of these components affect loop behavior and must be ac counted for in the loop compensation The mo...

Page 24: ...in one of three ways measured directly from a breadboard or if the appropriate parasitic values are known simulated or generated from the modulator transfer function Mea surement will give more accur...

Page 25: ...ossoverfrequencyabout25 of the switching frequency for maximum bandwidth Al though it may be tempting to go beyond fSW 4 remember that significant phase shift occurs at half the switching frequency th...

Page 26: ...frequency operation To prevent forcing current back into the main power supply potentially boosting the input supply to a dangerous voltage level forced continuous modeofoperationisdisabledwhentheTRAC...

Page 27: ...asheetstypicallyspecifynominalandmaximumvalues forRDS ON butnotaminimum Areasonableassumption is that the minimum RDS ON lies the same percentage below the typical value as the maximum lies above it C...

Page 28: ...eedback divider shown in Figure 16 In this tracking mode VOUT1 mustbesethigherthanVOUT2 Toimplement the ratiometric tracking the ratio of the divider should be exactly the same as the master IC s feed...

Page 29: ...the shifted common mode voltage The top two current sources are of the same amplitude In the coincident mode the TRACK SS voltage is substantially higher than 0 8V at steady state and effectively turn...

Page 30: ...example if RDS ON 0 01 andRL 0 005 thelosswillrangefrom15mW to 1 5W as the output current varies from 1A to 10A 2 Transition loss This loss arises from the brief amount of time the top MOSFET spends i...

Page 31: ...teepropercurrentlimitatworst caseconditions increasenominalVSNS byatleast50 to320mV bytying VRNG to 2V To check if the current limit is acceptable at VSNS 320mV assume a junction temperature of about...

Page 32: ...e layer should not have any traces and it should be as close as possible to the layer with power MOSFETs Place CIN COUT MOSFETs D1 and inductor all in one compact area It may help to have some compone...

Page 33: ...to ensure proper opera tion of the controller Segregate the signal and power grounds All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to...

Page 34: ...k LTC3810 5 EXTVCC TG SENSE BG BGRTN DRVCC INTVCC NDRV BOOST 38105 TA03 CB 0 1 F CDRVCC 0 1 F CVCC 1 F RUV2 61 9k RUV1 470k RON 110k DB BAS19 M1 Si7850DP M2 Si7850DP C5 22 F D1 B1100 COUT 47 F 6 3V 3...

Page 35: ...100pF CSS 1000pF VIN 15V TO 60V VOUT 3 3V 5A M3 ZVN4210G CC2 47pF RC 200k RFB2 3 24k RFB1 10 2k LTC3810 5 EXTVCC TG SENSE BG BGRTN DRVCC INTVCC NDRV BOOST 38105 TA04 CB 0 1 F CDRVCC 0 1 F CVCC 1 F RO...

Page 36: ...NT SHALL NOT EXCEED 0 20mm ON ANY SIDE 5 EXPOSED PAD SHALL BE SOLDER PLATED 6 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK NOTE 6 0 40 0 10 31 1 2...

Page 37: ...circuits as described herein will not infringe on existing patent rights Revision History REV DATE DESCRIPTION PAGE NUMBER D 12 10 Change to Operating Temperature Range Updated Order Information tabl...

Page 38: ...Down DC DC Controller PLL Fixed Frequency 100kHz to 600kHz 4V VIN 100V 0 8V VOUT 0 93VIN SSOP 16 SSOP 28 LT3845A 60V Low IQ Single Output Synchronous Step Down DC DC Controller Adjustable Fixed Frequ...

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