LTC2944
16
2944fa
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www.linear.com/LTC2944
FROM MASTER TO SLAVE
S
W
ADDRESS
REGISTER
DATA
FROM SLAVE TO MASTER
2944 F06
A: ACKNOWLEDGE (LOW)
A
: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W
: WRITE BIT (LOW)
A
A
A
0
1100100
01h
FCh
0
0
0
P
Figure 6. Writing FCh to the LTC2944 Control Register (B)
into the desired register. The transmission is ended when
the master sends a STOP condition. If the master contin-
ues by sending a second data byte instead of a stop, the
LTC2944 acknowledges again, increments its address
pointer and latches the second data byte in the following
register, as shown in Figure 7.
applicaTions inForMaTion
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 8. The LTC2944
acknowledges and the master sends a command byte
which indicates which internal register the master is to
read. The LTC2944 acknowledges and then latches the
S
W
ADDRESS
REGISTER
DATA
2944 F07
A
A
A
0
1100100
02h
F0h
01h
0
0
0
0
P
DATA
A
S
W
ADDRESS
REGISTER
Sr
2944 F08
A
A
ADDRESS
0
1100100
00h
1
0
0
1100100
0
P
R
1
A
01h
DATA
A
S
W
ADDRESS
REGISTER
Sr
2944 F09
A
A
ADDRESS
0
1100100
08h
1
0
0
1100100
0
P
R
0
A
F1h
DATA
24h
DATA
A
1
A
command byte into its internal register address pointer.
The master then sends a repeated START condition fol-
lowed by the same seven bit address with the R/W bit
now set to one. The LTC2944 acknowledges and sends
the contents of the requested register. The transmission
is ended when the master sends a STOP condition. If
the master acknowledges the transmitted data byte, the
LTC2944 increments its address pointer and sends the
contents of the following register as depicted in Figure 9.
Alert Response Protocol
In a system where several slaves share a common inter-
rupt line, the master can use the alert response address
(ARA) to determine which device initiated the interrupt
(Figure 10).
The master initiates the ARA procedure with a START
condition and the special 7-bit ARA bus address (0001100)
followed by the read bit (R) = 1. If the LTC2944 is as-
serting the
ALCC
pin in alert mode, it acknowledges and
responds by sending its 7-bit bus address (1100100)
and a 0. While it is sending its address, it monitors the
SDA pin to see if another device is sending an address at
the same time using standard I
2
C bus arbitration. If the
LTC2944 is sending a 1 and reads a 0 on the SDA pin on
the rising edge of SCL, it assumes another device with a
lower address is sending and the LTC2944 immediately
aborts its transfer and waits for the next ARA cycle to try
again. If transfer is successfully completed, the LTC2944
will stop pulling down the
ALCC
pin and will not respond
to further ARA requests until a new Alert event occurs.
Figure 7. Writing F001h to the LTC2944 Accumulated Charge
Register (C, D)
Figure 8. Reading the LTC2944 Status Register (A)
Figure 9. Reading the LTC2944 Voltage Register (I, J)
