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dc2151af

DEMO MANUAL DC2151A

Quick start proceDure

Using short twisted pair leads for any power connections, 

with all loads and power supplies off, refer to Figure 4 for 

the proper measurement and equipment setup. 
Follow the procedure below:
1.  Before connecting PS1 to the DC2151A, PS1 must have 

its current limit set to 300mA and PS2 must have its 

current limit set to 100mA. For most power supplies 

with a current limit adjustment feature the procedure 

to set the current limit is as follows. Turn the voltage 

and current adjustment to minimum. Short the output 

terminals and turn the voltage adjustment to maximum. 

Adjust the current limit to 300mA for PS1 and 100mA 

for PS2. Turn the voltage adjustment to minimum and 

remove the short between the output terminals. The 

power supply is now current-limited to 300mA and 

100mA respectively.

2.  Initial Jumper, PS and LOAD settings:
  JP1 = 0 

JP2 = 0 

JP3 = 0 

JP4 = 0 

  JP5 = 0 

JP6 = 0 

JP7 = 0 

JP8 = 0 

  JP9 = 0 

JP10 = 0 

  JP11 = RUN  JP12 = OFF 
  PS1 = OFF  PS2 = OFF  LOAD1 = OFF 

Remove battery from battery holder 

  

3.  Connect PS1 to the V

IN

 Terminals, then turn on PS1 

and slowly increase voltage to 2.0V while monitoring 

the input current. If the current remains less than 5mA, 

increase PS1 to 5.0V.

4.  Set LOAD1 to 50mA. Verify voltage on V

OUT

 is within the 

V

OUT

 1.8V range listed in the Performance Summary. 

Verify that the output ripple voltage is between 10mV 

and 50mV.  Verify  that  PGV

OUT

  is  high.  Decrease 

LOAD1 to 5mA. Verify that PGV

OUT

 and EH_ON are 

high. Decrease PS1 to 2.0V. Verify that V

OUT

 is 0V.

5.  Set JP1, JP2, JP3, JP4 to 1. Slowly increase PS1 to 

16V and verify that V

OUT

 is off. Increase PS1 to 19V 

and verify that V

OUT

 is within the V

OUT

 1.8V range listed 

in the Performance Summary. Decrease PS1 to 4.0V. 

Verify that V

OUT

 is 0V.

6.  Decrease PS1 to 0V and disconnect PS1 from V

IN

. Set 

the current limit of PS1 to 25mA as described above.

7.  Move the connection for PS1 from V

IN

 to AC1. Slowly 

increase  PS1  voltage  to 2.0V  while  monitoring  the 

input current. If the current remains less than 5mA, 

increase PS1 to 19V. Verify voltage on V

OUT

 is within 

the V

OUT

 1.8V range listed in the Performance Sum-

mary. Decrease PS1 to 0V, swap the AC1 connection 

to AC2 and repeat the test. Decrease PS1 to 0V and 

move the connection for PS1 from AC2 to V

IN

.

8.  Set JP5 to 1, JP6 to 1, and JP7 to 1. Increase PS1 to 

19V and set LOAD1 to 50mA. Verify voltage on V

OUT

 is 

within the V

OUT

 5.0V range listed in the Performance 

Summary. Verify that the output ripple voltage is be-

tween 40mV and 90mV. Set PS1 to 0V.

9.  Set  the  current  limit  of  PS2  to 60mA  as  described 

above. Set JP1 to 0, JP2, JP3 and JP4 to 1, JP5–JP7 

to 1 and JP8–JP10 to 0. Set JP12 to CHARGE. Increase 

PS1 to 12V and set LOAD1 to 0mA. Connect PS2 to 

the BAT_IN Terminals, then turn on PS2 and slowly 

increase voltage to 1.0V while monitoring the input 

current. If the current remains less than 15mA, increase 

PS2 until V

M4

 reads 2.7V. Verify that the current in 

AM2 is approximately 660µA. Increase PS2 to 3.5V 

and verify that V

M4

 is approximately 3.45V. 

10. Set JP8–JP10 to 1. Increase PS1 to 12V and set LOAD1 

to 0mA. Set PS2 to 3.7V. Verify that the current in 

AM2 is approximately 330µA. Increase PS2 to 4.3V 

and verify that V

M4

 is approximately 4.2V. 

11. Set JP12 to FAST_CHRG. Set PS2 to 3.7V. Verify that 

the current in AM2 is approximately 10mA. Set JP12 

to CHARGE

12. Set the current limit of PS2 to 100mA as described 

above. Set PS1 to 14V. Set JP1 to 1, JP2, JP3 and 

JP4 to 0, JP5 to 0, JP6 and JP7 to 1. Set JP8 to 0. Set 

PS2 to 3.2V. Set LOAD1 to 5mA. Remove PS1 lead 

from the V

IN

 turret. Verify voltage on V

OUT

 is within 

the V

OUT

 3.0V range listed in  Performance Summary. 

Verify that PGV

OUT

 is high and EH_ON is low. Decrease 

PS2 to 2.6V and verify that V

OUT

 is 0V. Increase PS2 to 

3.8V. Press and release PB1. Verify the V

OUT

 is 3.0V.

Summary of Contents for DC2151A

Page 1: ...ernative energy applications The energy harvesting power supply consisting of an integrated low loss full wave bridge with a high voltage buck converter harvests energy from piezoelectric solar ormagn...

Page 2: ...gapplica tions It is designed to interface directly to a piezoelectric or alternative A C energy source rectify and store the har vestedenergyonanexternalcapacitorwhilemaintaininga regulated output vo...

Page 3: ...shunt regulator which can sink up to 10mA The battery float voltage is programmable with two bits and a third bit is used to program the battery connect and disconnectvoltagelevels Thisdisconnectfeat...

Page 4: ...Set the current limit of PS1 to 25mA as described above 7 Move the connection for PS1 from VIN to AC1 Slowly increase PS1 voltage to 2 0V while monitoring the input current If the current remains less...

Page 5: ...ess and release PB1 Verify the VOUT is 3 0V 14 SetJP11toSHIPandverifythatVOUTisapproximately0V 15 Decrease PS2 to 0V and disconnect PS2 16 Set the current limit of PS1 to 300mA as described above Conn...

Page 6: ...en the LTC3331 and the Dust Mote Remove the battery from the BH1 holder on the bottom side of the DC2151A On the DC2151A set JP1 to 1 JP2 to 0 JP3 to 1 JP4 to 0 JP5 to1 JP6 to 0 JP7 to 0 JP8 JP9 and J...

Page 7: ...eing recharged from the V25W piezoelectric transducer The input capacitor is charging from 4 48V to 5 92V in 208 milliseconds The power delivered from the V25W is 648 W PCIN CIN VIN1 2 VIN2 2 2 t PCIN...

Page 8: ...of the output supercapacitor which takes approximately 3300 seconds The above calculation neglects the lower efficiency at low output voltages and the time it takes to transfer the energy from the inp...

Page 9: ...through many UVLO transitions to charge the output capacitor back up to the sleep threshold Once the output is charged to the output sleep threshold the EH_ON signal will again be consistently high i...

Page 10: ...VIN reaches its UVLO_FALLING threshold EH_ON will go 1F 2 7V 1F 2 7V LTC3331 DC2051A F13 AC1 VIN CAP VIN2 AC2 SWB SWA SW VOUT SCAP BAL PGVOUT EH_ON IPK2 IPK1 IPK0 OUT2 OUT0 OUT1 VIN3 0 1 F 6 3V UVLO...

Page 11: ...the PGVOUT threshold for the VOUT setting of 3 6V When a pulse load is applied that is greater than the energy supplied by the input capacitor VIN will drop below the VIN_UVLO_FALLING threshold EH_ON...

Page 12: ...MOTE FOR WIRELESS MESH NETWORKS PGOOD EHORBAT TX VSUPPLY GND VOUT 3 6V FOR EH_ON 1 VOUT 2 5V FOR EH_ON 0 100 F 6 3V 22 H 22 H FOR PEAK POWER TRANSFER CENTER THE UVLO WINDOW AT HALF THE RECTIFIED OPEN...

Page 13: ...TRPBF Additional Demo Board Circuit Components 1 0 C8 C9 CAP CHIP X5R 0 1 F 10 10V 0402 OPT TDK C1005X5R1A104K 2 0 C10 SUPERCAP ULTRACAPACITOR 330mF 5 5V 60m DOUBLE CELL MURATA DMF3R5R5L334M3DTA0 3 1...

Page 14: ...Y TO LINEAR TECHNOLOGY AND SCHEMATIC SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS SCALE NONE www linear com 2 DEMO CIRCUIT 2151A 1 2 NANOPOWER BUCK BOOST DC DC N A LTC3331EUH NC JD 2 21 14 WITH ENERG...

Page 15: ...T EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS HOWEVER IT REMAINS THE CUSTOMER S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION COMPONENT SU...

Page 16: ...DING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONS...

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