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dc1884af

DEMO MANUAL DC1884A

QUICK START PROCEDURE

Setup

If a DC1371 data acquisition and collection system was 
supplied with the DC1884, follow the DC1371 Quick Start 
Guide to install the required software and to connect the 
DC1371 to the DC1884 and to a PC.

DC1884 Board Jumpers

The DC1884 board should have the following jumper set-
tings as default positions (as per Figure 1):

JP14: PAR/SER:

 Selects Parallel or Serial Programming 

Mode. (Default: Serial)

Optional Jumpers AJ3 and J6: Term:

 Enables/Disable 

Optional Output Termination. (Default: Removed)

JP5: I

LVDS

:

 Selects Either 1.75mA or 3.5mA of Output 

Current for the LVDS Drivers. (Default: Removed)

JP1 and JP2: Lane:

 Selects Either 1-Lane or 2-Lane Output 

Modes (Default: Removed) 

Note: The DC1371 does not support 1-Lane operation.

JP9: SHDN:

 Enables and Disables the LTM9011. 

(Default: Removed)

JP8: WP:

 Enable/Disables Write Protect for the EEPROM. 

(Default: Removed)

Note:  Optional jumper should be left open to ensure proper 
serial confi guration.

Applying Power and Signals to the DC1884 

The DC1371 is used to acquire data from the DC1884. The 
DC1371 must fi rst be connected to a powered USB port 
and have 5V applied power before applying 3.5V across 
the pins marked V

+

 and “GND” on the DC1884. DC1884 

requires 3.5V for proper operation.

The DC1884 demonstration circuit requires up to 700mA 
depending on the sampling rate and the A/D converter 
supplied.

The DC1884 should not be removed or connected to the 
DC1371 while power is applied.

Analog Input Network

For optimal distortion and noise performance, the RC 
network on the analog inputs may need to be optimized 
for different analog input frequencies. For input frequen-
cies above 70MHz, refer to the LTM9011 data sheet for a 
proper input network. 

In almost all cases, fi lters will be required on both analog 
input and encode clock to provide data sheet SNR.  

The fi lters should be located close to the inputs to avoid 
refl ections from impedance discontinuities at the driven 
end of a long transmission line. Most fi lters do not present 
50Ω outside the passband. In some cases, 3dB to 10dB 
pads may be required to obtain low distortion. 

If your generator cannot deliver full-scale signals without 
distortion, you may benefi t from a medium power amplifi er 
based on a gallium arsenide gain block prior to the fi nal 
fi lter. This is particularly true at higher frequencies where 
IC based operational amplifi ers may be unable to deliver 
the combination of low noise fi gure and high IP3 point 
required. A high order fi lter can be used prior to this fi nal 
amplifi er, and a relatively lower Q fi lter used between the 
amplifi er and the demonstration circuit. 

Summary of Contents for DC1884A Series

Page 1: ...ode Sampling Frequency Convert Clock Frequency See Table 1 Encode Clock Level Single Ended Encode Mode ENC Tied to GND 0V to 3 6V Encode Clock Level Differential Encode Mode ENC Not Tied to GND 0 2V t...

Page 2: ...formance of the LTM9011 family of A D converters For proper mea surement equipment setup refer to Figure 1 and follow the procedure explained in the following sections Figure 1 Test Setup of DC1884 DC...

Page 3: ...and GND on the DC1884 DC1884 requires 3 5V for proper operation The DC1884 demonstration circuit requires up to 700mA depending on the sampling rate and the A D converter supplied The DC1884 should n...

Page 4: ...harmonically related spurs and broadband noise Low phase noise Agilent 8644B generators are used for both the clock input and the analog input Digital Outputs Data outputs data clock and frame clock s...

Page 5: ...Off Default Disables data output randomizer On Enables data output randomizer Two s Complement Enables Two s Complement Mode Off Default Selects offset binary mode On Selects two s complement mode Sle...

Page 6: ...nternalTermination EnablesLVDSInternalTermination Off Default Disables internal termination On Enables internal termination Outputs Enables Digital Outputs Enabled Default Enables digital outputs Disa...

Page 7: ...JP8 JP9 HEADERS SGL ROW 3 PINS 2mm CTRS SAMTEC TMM 103 02 L S 15 10 J1 J2 J4 J5 J6 J7 J8 J9 J10 J11 CON SMA STRAIGHT CONNEX 132134 16 1 J3 BGA CONN 10 40 PIN SAMTEC SEAM 40 02 0 S 10 2 A K TR 17 0 L1...

Page 8: ...8 MICROCHIP 24LC32A I ST 37 8 AS SHOWN ON ASSY DWG SHUNT 0 079 CENTER SAMTEC 2SN BK G STENCIL TOP AND BOTTOM DC1884 1 DC1884A A 1 1 DC1884A 1 GENERAL BOM 2 1 U1 IC AD CONVERTER MODULE BGA140 11 25mm 9...

Page 9: ...E WITH LINEAR TECHNOLOGY PARTS SCALE NONE www linear com 1 DEMO CIRCUIT 1884A 03 16 2012 04 46 PM 1 3 LOW POWER OCTAL ADC B LTM90XXIY KIM T CLARENCE M REVISION HISTORY DESCRIPTION DATE APPROVED ECO RE...

Page 10: ...2pF C102 8 2pF T4 MABAES0060 T4 MABAES0060 4 5 1 3 2 C96 8 2pF C96 8 2pF R124 49 9 R124 49 9 R173 10 0201 R173 10 0201 C74 8 2pF C74 8 2pF T6 MABAES0060 T6 MABAES0060 4 5 1 3 2 R130 10 R130 10 C92 4...

Page 11: ...D35 3P3V D36 GND D37 3P3V D38 GND D39 3P3V D40 J3H SEAM 10X40PIN J3H SEAM 10X40PIN VREF_A_M2C H1 PRSNT_M2C_N H2 GND H3 CLK0_M2C_P H4 CLK0_M2C_N H5 GND H6 LA02_P H7 LA02_N H8 GND H9 LA04_P H10 LA04_N H...

Page 12: ...UDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CON...

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