Linear Technology DC1762A, Demo Manual

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dc1762afb
DEMO MANUAL DC1762A
Description
LTC2165, LTC2164, LTC2163
LTC2162, LTC2161, LTC2160, LTC2159, LTC2269
16-Bit, 20Msps to125Msps ADCs
Demonstration circuit 1762A supports a family of 16-Bit
20Msps to 125Msps ADCs. Each assembly features one
of the following devices: LTC
®
2165, LTC2164, LTC2163,
LTC2162, LTC2161, LTC2160, LTC2159, or LTC2269 high
speed, high dynamic range ADCs.
Demonstration circuit 1762A supports the LTC2165 family
DDR LVDS output mode.
The versions of the 1762A demo board supporting the
LTC2165 series of A/D converters are listed in Table 1.
L
, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and PScope is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Depending on the required resolution and sample rate,
the DC1762A is supplied with the appropriate ADC. The
circuitry on the analog inputs is optimized for analog input
frequencies from 5MHz to 140MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
Table 1. DC1762A Variants
DC1762A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY
1762A-A LTC2165 16-Bit 125Msps 5MHz to 140MHz
1762A-B LTC2164 16-Bit 105Msps 5MHz to 140MHz
1762A-C LTC2163 16-Bit 80Msps 5MHz to 140MHz
1762A-D LTC2162 16-Bit 65Msps 5MHz to 140MHz
1762A-E LTC2161 16-Bit 40Msps 5MHz to 140MHz
1762A-F LTC2160 16-Bit 25Msps 5MHz to 140MHz
1762A-G LTC2159 16-Bit 20Msps 5MHz to 140MHz
1762A-H LTC2269 16-Bit 20Msps 5MHz to 140MHz
performance summary
(T
A
= 25°C)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage – DC1762A Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 500mA.
4.5 6 V
Analog Input Range Depending on SENSE Pin Voltage 1 2 V
P-P
Logic Input Voltages Minimum Logic High
Maximum Logic Low
1.3
0.6
V
V
Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
350
1.25
247
1.25
mV
V
mV
V
Sampling Frequency (Convert Clock Frequency) See Table 1
Convert Clock Level Single-Ended Encode Mode (ENC
–
Tied to GND)
Differential Encode Mode (ENC
–
Not Tied to GND)
0
0.2
3.6
3.6
V
V
Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet