LT8708
48
Rev 0
For more information
Figure 18. Switches Layout
• Avoid running signal traces parallel to the traces that
carry high di/dt current because they can receive
inductively coupled voltage noise. This includes the
SW1, SW2, TG1 and TG2 traces to the controller.
• Use immediate vias to connect the components (in-
cluding the LT8708’s GND pins) to the ground plane.
Use several vias for each power component.
• Minimize parasitic SW pin capacitance by removing
GND, V
IN
and V
OUT
copper from underneath the SW1
and SW2 regions.
• Except under the SW pin regions, flood all unused
areas on all layers with copper. Flooding with copper
will reduce the temperature rise of power components.
Connect the copper areas to a DC net (i.e., quiet GND)
with many vias. The more vias the board has, the better
heat conduction it has.
• Partition the power ground from the signal ground.
The small-signal component grounds should not return
to the IC GND through the power ground path.
• Place switch M2 and switch M3 as close to the
controller as possible, keeping the GND, BG and SW
traces short.
• Minimize inductance from the sources of M2 and M3
to R
SENSE
by making the trace short and wide.
• Keep the high dv/dt nodes SW1, SW2, BOOST1,
BOOST2, TG1 and TG2 away from sensitive small-
signal nodes.
• The output capacitor (–) terminals should be connected
as closely as possible to the (–) terminals of the input
capacitor.
• Connect the top driver boost capacitor C
B1
closely to the
BOOST1 and SW1 pins. Connect the top driver boost
capacitor C
B2
closely to the BOOST2 and SW2 pins.
• Connect the C
IN
and C
OUT
capacitors closely to the
power MOSFETs. These capacitors carry the MOSFET
AC current in the boost and buck regions.
• Connect the FBOUT, FBIN, VINHIMON and VOUTLO-
MON pin resistor dividers to the (+) terminals of C
OUT
and C
IN
, respectively. Small FBOUT/FBIN/VINHIMON/
VOUTLOMON bypass capacitors may be connected
closely to the LT8708’s GND pin if needed. The resistor
connections should not be along the high current or
noise paths.
• Route current sense traces (CSP/CSN, CSPIN/CSNIN,
CSPOUT/CSNOUT) together with minimum PC trace
APPLICATIONS INFORMATION
GND
V
OUT
C
OUT
L
R
SENSE
8708 F18
M4
M3
M2
M1
SW1
SW2
D2
D4
D1
V
IN
C
IN
LT8708
CKT
D3
M3
M4
M1
M2
LT8708
CKT
D4
D2
D1
D3
V
OUT
V
IN
SW1
SW2
L
R
SENSE
GND
C
OUT
C
IN
18(a)
18(b)
