LG MG210, Service Manual, Page: 29 / 127

3.5.3. Audio uplink processing
The VUL path includes two input stages. The first stage is a microphone amplifier, compatible with
electret microphones containing a FET buffer with open drain output. The microphone amplifier has a
gain of typically 25.6 dB (
±
1 dB) and provides an external voltage of 2.0 V or 2.5 V to bias the
microphone (MICBIAS). The auxiliary audio input can be used as an alternative source for higher level
speech signals. This stage performs single-ended-to differential conversion and provides a
programmable gain of 4.6 dB or 28.2 dB. The third stage is a headset microphone amplifier,
compatible with electret microphones. The headset microphone amplifier has a gain of typically 18 dB
and provides an external voltage of 2.0 V or 2.5 V to bias the headset microphone (HSMICBIAS).
When one of the input stages (MICI, AUXI, HSMICP) is in use, the two other input stages are disabled
and powered down. The resulting fully differential signal is fed to the analog-to-digital converter (ADC).
The ADC conversion slope depends on the value of the internal voltage reference. Analog-to-digital
conversion is performed by a third-order
Σ
-
∆
modulator with a sampling rate of 1 MHz. Output of the
ADC is fed to a speech digital filter, which performs the decimation down to 8 kHz and band-limits the
signal with both low-pass and high-pass transfer functions. Programmable gain can be set digitally
from -12 dB to +12 dB in 1-dB steps and is programmed with bits 4-0 (VULPG(4:0)) of the voiceband
uplink register. The speech samples are then transmitted to the DSP via the VSP at a rate of 8 kHz.
There are 15 meaningful output bits. Programmable functions of the VUL path, power-up, input
selection, and gain are controlled by the BSP or the USP via the serial interfaces. The VUL path can
be powered down by bit 0 (VULON) of the power down register.
3. H/W Circuit Description
- 28 -
Figure 11. Uplink Path
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