3. TECHNICAL BRIEF
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Only for training and service purposes
LGE Internal Use Only
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3.5 LO GENERATION and DISTRIBUTION CIRCUIT
TX LO
The Tx LO frequency synthesizer generates the transmit LO signals, and then distribution circuits deliver the
quadrature LO to the upconverters. All PLL circuits are on-chip, including the oscillating signal sources,
digital PLL circuits, and circuits for adjusting the GSM transmit phase. External circuits are not required, not
even an RC network for the loop filter. A high-level functional block diagram is shown right.
The buffered 19.2 MHz XO signal is frequency-multiplied and then used as the synthesizer input (REF), the
frequency reference to which the PLL is phase and frequency locked. Another PLL input varies as the loop
acquires lock, and is generated by counting the oscillator output pulses (at FDBK). The closed-loop will force
the oscillator output to match the programmed value. If the loop is not locked, the error between inputs
creates an error signal at the output of the PLL. This error signal tunes the output frequency so that the error
is decreased. Ultimately, the loop forces the error to approach zero and the PLL is phase and frequency
locked. The UHF output of the transmit LO synthesizer feeds a distribution network that drives the active
upconverter LO ports with the appropriate frequency and amplitude. The LO signals applied to the
upconverter are differential with a quadrature phase relationship. During GSM operation, the phase is
dynamically adjusted using a 5-line digital interface with the digital baseband circuits. The GSM phase-adjust
circuitry also uses the frequency-multiplied reference signal.
[Figure 3-11] MDM TX LO circuits
