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LGE Internal Use Only
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
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3.2 GSM Part
3.2.1 GSM Receiver
The LG-S310 receiver section fully integrates all the RF and baseband signal processing. Each block is
described in the following sections.
[Figure 4.2.1-1] GSM Receiver Path
Low Noise Amplifiers
The LNAs have differential inputs which help minimize the effect of unwanted interferers. The inputs are
easily matched to industry standard FEMs or discrete Rx SAW filters. The outputs of the LNAs are directly
coupled to the down-converting mixers. The voltage gain of the LNAs is typically 24 dB. Each LNA can be
switch to a low gain mode when receiving large input signals as part of the AGC system.
Down-Converting Mixers
Two quadrature mixers are used to mix down the signals from the LNAs, one for the high bands (1800 and
1900 MHz) and one for the low bands (850 and 900 MHz). The outputs of the mixers are connected to the
baseband section through an integrated single pole filter with nominal cut-off frequency of 800kHz. This acts
as a “roofing filter” for the largest blocking signals (i.e. those ≥ 3MHz) and prevents the baseband amplifiers
from being overloaded.
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The translation loop modulator and Tx VCO are extremely low noise removing the need for external TX
filtering. To support EDGE modulation with high PA efficiency the design includes a full polar modulation
architecture including PA linearization. To reduce BOM the TX PLL loop filter components are fully integrated.
The AD6546 uses the industry proven direct conversion receiver architecture of the Othello
TM
family. For
Quad band applications the front End features four fully integrated differential LNAs with programmable-
gain. The RF is downconverted by quadrature mixers and then fed to the baseband programmable-gain
amplifiers and active low pass filters for channel selection. The programmable-gain baseband amplifiers and
the LNA gain step are set via a standard 3-wire serial bus. The Receiver output pins can be directly connected
to the baseband analog processor. The Receive path features automatic calibration and tracking to remove
DC offsets. The AD6546 uses a single integrated LO VCO for both receive and the transmit paths. The
synthesizer lock times are optimized for EGPRS applications up to and including class 12. The AD6546
contains three on-chip low dropout voltage regulators(LDOs). These maintain the correct supply voltages to
the on chip circuits with a wide range of battery voltage input. Comprehensive power down options are
included to minimize power consumption in normal use.
