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Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. CIRCUIT DIAGRAM
75
FB100
R100
0
I
N
D
91
1
R
U100
bga130p_p_65w8x9h1_0_r
EUSY0425901
B6
B3
B4
A4
A7
A3
A6
M8
L7
M7
N5
N4
M4
N3
N2
L8
M6
L6
N7
L5
M3
M2
M1
H7
D5
H8
D7
J1
G2
F2
H2
D3
F8
G8
B7
B8
C7
C8
C6
D8
C5
E6
J5
J7
K8
J8
K7
K6
K5
K4
J2
H3
E1
E2
J3
C4
D2
C3
D1
C2
B2
K3
K2
K1
J4
N9
N6
M10
L9
L2
K10
J10
H9
H1
G9
F10
E9
D10
C9
B10
B5
B1
A9
M5
A5
L4
L3
J6
H6
H5
H4
G7
G6
G5
G4
G3
F7
F6
F5
F4
F3
F1
E8
E7
E5
E4
E3
D6
D4
A2
M9
L10
K9
J9
H10
F9
E10
D9
C10
B9
N8
L1
G10
G1
C1
A8
0
1
N
1
N
0
1
A
1
A
1
C
N
6
2
C
N
8
2
C
N
9
2
C
N
VDD1
VDD2
VDD3
VDD5
VDD4
VDD6
VDDQ1
VDDQ6
VDDQ5
VDDQ4
VDDQ10
VDDQ9
VDDQ2
VDDQ8
VDDQ7
VDDQ3
NC27
NC20
NC21
NC9
NC19
NC8
NC11
NC12
NC17
NC18
NC7
NC16
NC25
NC6
NC10
NC5
NC13
NC14
NC4
NC2
NC24
NC22
NC23
NC15
NC3
VCC1
VCC2
VSS1
VSS4
VSS8
VSSQ5
VSSQ4
VSSQ9
VSSQ8
VSSQ3
VSS2
VSS3
VSSQ10
VSSQ1
VSSQ2
VSS5
VSSQ6
VSSQ7
VSS6
VSS7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CK
CK
CKE
/CS
/RAS
/CAS
/WED
UDQM
LDQM
UDQS
LDQS
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
/CE
/RE
/WE
CLE
ALE
/WP
R/B
C119
1u
C147
22p
CN100
9
8
7
6
5
4
3
2
1
OJ102
OJ101
Q100
EBK61572201
LSCR523EBFS8
2
1
3
OJ103
TP111
VRTC
C108
10u
C149
0.1u
TP112
TP114
UA100
12
11
10
9
8
7
6
5
4
3
2
1
GND
RX
TX
NC1
ON_SW
VBAT
NC2
NC3
NC4
DSR
RTS
CTS
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
3G
2.5G
VBAT
R117
1K
VBUS_USB
R118
100K
0.1u
C133
C125
0.1u
C123
0.1u
0.1u
C124
C135 0.1u
VDD_IO_1V8
VDD_IO_1V8
I
N
D
60
1
R
VDD_IO_1V8
VDD_IO_1V8
I
N
D
90
1
R
I
N
D
01
1
R
K7.
4
80
1
R
K7.
4
70
1
R
C150
0.1u
X101
EXXY0018701
FC-135
32.768KHz
21
C132
1u
1u
C126
C131
0.1u
0.1u
C130
C129
0.1u
0.1u
C127
C140
1n
47p
C143
C142
47p
47p
C139
C138
47p
DNI
C137
DNI
C136
VMAIN_MIC
VDD_IO_1V8
C141
1n
VHS_MIC
220n
C146
C148
22p
X100
EXXY0027001
DSX321G-26M
26MHz
2
1
3
4
51
1
R
K2.
2
K2.
2
41
1
R
VDD_IO_1V8
R111
100K
R112
100K
R113
100K
VSIM_2V85
C134
0.1u
VDDTRX
C128 4.7n
VBAT
CT
R
V
1F
R
V
2F
R
D
D
V
1
V3
_
B
S
U
V
58
V2
_
C
M
M
V
58
V2
_
X
U
A
V
2F
R_
T
A
B
V
3
V1
_
U
M
P
V
8
V1
_
OI
_
D
D
V
8
V1
_
OI
_
D
D
V
8
V1
_
OI
_
D
D
V
8
V1
_
OI
_
D
D
V
VBAT
C122
10u
C121
22u
5.6K
R104
R102
3.9K
O
X
D
D
V
VBAT
3.3u
00
1L
100K
R103
S
M
D
D
V
2
V1
_
E
R
O
C
V
470
R101
8
V1
_
OI
_
D
D
V
C
DT
D
D
V
8
V1
_
OI
_
D
D
V
VDD_IO_1V8
2
V1
_
E
R
O
C
V
C102
2.2u
VDD_IO_1V8
VDD_IO_1V8
VUSB_3V1
VBAT
VCORE_1V2
VDDMS
VDDTRX
VDD_IO_1V8
C117
0.1u
VDD_IO_1V8
VDDRF2
VDDTDC
VMMC_2V85
VDD_IO_1V8
VRF1
C106
0.1u
VAUX_2V85
0.1u
C103
1u
C115
VDDXO
C101
2.2u
4.7n
C112
470n
C105
VBAT_RF2
470n
C120
47n
C114
47n
C113
VPMU_1V3
VBAT
0.1u
C118
VBAT
C109
1u
C100
0.1u
220n
C107
220n
C111
470n
C104
18p
C110
C116
1u
U101
EUSY0429401
8
K
7
T
8
R
9
M
6
T
8
M
8
L
2
1
L
7
1
C
7
1
F
2
1
H
5
1
G
1
1
M
9
L
4
1
F
0
1
P
4
1
E
6
1
G
8
1
R
4
1
B
PMB8815
3
1
E
5
1
H
4
1
G
5
1
A
2
1
J
5
1
F
6
1
F
7
1
P
6
1
P
0
1
G
0
1
K
7
R
1
1
J
1
1
H
0
1
F
3
A
1
1
T
2
1
P
8
H
6
P
6
F
9
K
1
1
G
0
1
N
8
1
P
3
1
L
6
1
L
9
R
9
T
8
T
9
P
T12
P13
R12
P15
P14
T15
R15
T14
R14
N17
N18
T16
R16
M18
M17
K17
P11
P4
J4
T2
J5
G1
L4
J3
L2
P5
P2
J8
T5
P1
T4
R6
R2
N2
B1
A2
G6
H4
H2
G2
G3
H3
H1
H6
K4
K2
J1
K3
L3
J2
M2
L1
M3
R1
P7
N6
N4
L5
M5
T3
R4
R3
P3
M1
M4
N3
N5
R5
L11
K12
L10
G12
H13
J13
F13
G13
C6
J14
J15
K18
H17
H18
G18
J18
J17
H14
E1
G4
G5
F2
F3
F1
D2
D1
E2
M10
A13
B13
K14
K13
B4
A5
B5
A4
J10
H9
J9
H10
B16
C14
B17
B18
C15
B15
C16
E18
F18
C18
D18
A16
A17
R17
T17
M13
M12
N13
R13
T13
N14
1
1
F
1
T
8
1
T
8
1
A
1
A
1
1
R
7
A
7
B
0
1
C
0
1
B
0
1
A
0
1
D
6
B
5
1
L
7
1
L
8
1
L
6
A
0
1
R
0
1
T
2
1
F
1
1
E
1
1
C
1
1
B
1
1
D
2
1
E
2
1
D
2
1
C
2
1
B
2
1
A
1
1
A
8
E
9
G
8
F
9
E
9
F
8
G
0
1
E
9
C
8
C
9
B
9
A
7
C
8
B
8
A
2
B
2
C
4
E
6
D
5
C
5
E
5
F
1
C
4
D
3
B
3
C
4
C
5
D
4
F
3
D
3
E
0
D
_
F
I
D
1
D
_
F
I
D
2
D
_
F
I
D
3
D
_
F
I
D
4
D
_
F
I
D
5
D
_
F
I
D
6
D
_
F
I
D
7
D
_
F
I
D
8
D
_
F
I
D
1
S
C
_
F
I
D
D
C
_
F
I
D
R
W
_
F
I
D
D
R
_
F
I
D
D
H
_
F
I
D
D
V
_
F
I
D
T
E
S
E
R
_
F
I
D
0
D
_
F
I
C
1
D
_
F
I
C
2
D
_
F
I
C
3
D
_
F
I
C
4
D
_
F
I
C
5
D
_
F
I
C
6
D
_
F
I
C
7
D
_
F
I
C
K
L
C
P
_
F
I
C
C
N
Y
S
H
_
F
I
C
C
N
Y
S
V
_
F
I
C
2
T
U
O
K
L
C
D
P
_
F
I
C
T
E
S
E
R
_
F
I
C
0
N
I
_
P
K
1
N
I
_
P
K
2
N
I
_
P
K
3
N
I
_
P
K
4
N
I
_
P
K
5
N
I
_
P
K
0
T
U
O
_
P
K
1
T
U
O
_
P
K
2
T
U
O
_
P
K
3
T
U
O
_
P
K
5
T
U
O
_
P
K
B
I
V
B
I
V
_
S
S
V
0
T
U
O
K
L
C
K
2
3
F
K
2
3
C
S
O
N
_
T
E
S
E
R
N
I
2
T
0
K
L
C
_
1
S
2
I
X
R
_
1
S
2
I
X
T
_
1
S
2
I
0
A
W
_
1
S
2
I
L
C
S
_
C
2
I
A
D
S
_
C
2
I
F
F
O
N
O
1
C
N
2
C
N
3
C
N
4
C
N
S
F
D
D
V
M0
M1
M2
VDD_FMR
FMRIN
FMRINX
CP1
CP2
TX1
FE2
RX12
RX12X
RX34
RX34X
VDET
PABS
PABIAS
FE1
TX2
PAEN
VDDTRX
USIF2_TXD_MTSR
USIF2_RXD_MRST
USIF2_RTS_N
USIF2_CTS_N
USIF1_TXD_MTSR
USIF1_RXD_MRST
USIF1_RTS_N
USIF1_CTS_N
DPLUS
DMINUS
XOX
XO
VSIM
SIM_IO
SIM_CLK
SIM_RST
MMCI_CMD
MMCI_DAT_0
MMCI_CLK
MMCI_DAT_1
MMCI_DAT_2
MMCI_DAT_3
SWIF_TXRX
TDO
TDI
TMS
TCK
TRST_N
TRIG_IN
MON1
MON2
MON3
FSYS1
FSYS2
DIGUP_CLK
DIGUP1
DIGUP2
LEDFBN
LEDFBP
LEDDRV
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
FWP
FCDP_RBn
CS0_n
CS1_n
CS2_n
ADV_n
RD_n
WR_n
WAIT_n
RAS_n
CAS_n
BC0_n
BC1_n
BC2_n
BC3_n
SDCLKO
BFCLKO_0
BFCLKO_1
CKE
ANAMON
FSYS_EN
EPN
EPP
HSL
HSR
LSN
LSP
MICN1
MICP1
MICN2
MICP2
VMIC
VUMIC
ACD
AGND
VREF
1
D
S
_
D
D
V
B
F
_
1
D
S
1
D
S
_
S
S
V
W
S
1
D
S
1
S
M
S
S
V
2
S
M
S
S
V
P
S
T
A
B
V
U
M
P
_
T
A
B
V
1
O
I
D
D
V
2
O
I
D
D
V
1
U
B
E
_
D
D
V
2
U
B
E
_
D
D
V
L
L
D
_
D
D
V
U
M
P
V
U
M
P
_
S
S
V
1
E
R
O
C
S
S
V
2
E
R
O
C
S
S
V
3
E
R
O
C
S
S
V
4
E
R
O
C
S
S
V
5
E
R
O
C
S
S
V
E
R
O
C
V
E
R
O
C
D
D
V
P
C
8
V
1
D
D
V
R
S
L
S
S
V
X
R
T
S
S
V
X
R
S
S
V
1
8
V
1
D
D
V
P
M
A
R
V
G
I
D
_
S
S
V
S
M
D
D
V
O
X
D
D
V
C
D
T
D
D
V
G
E
N
D
D
V
T
A
B
V
O
C
D
S
S
V
X
U
A
V
O
X
S
S
V
C
M
M
V
B
S
U
V
2
F
R
D
D
V
1
F
R
V
O
L
_
S
S
V
F
R
S
S
V
C
T
R
V
N
E
S
N
E
S
P
E
S
N
E
S
G
H
C
D
D
V
S
C
B
S
C
G
H
C
V
T
N
H
S
V
S
T
C
_
T
R
A
U
_
T
B
S
T
R
_
T
R
A
U
_
T
B
UART_RX
UART_RX
UART_RX
UART_TX
UART_TX
UART_TX
NANDD_DDRA[10]
NANDD_DDRA[10]
NANDD_DDRA[10]
NANDD_DDRA[11]
NANDD_DDRA[11]
NANDD_DDRA[11]
NANDD_DDRA[12]
NANDD_DDRA[12]
NANDD_DDRA[12]
NANDD_DDRA[13]
NANDD_DDRA[13]
NANDD_DDRA[14]
NANDD_DDRA[14]
NANDD_DDRA[14]
NANDD_DDRA[15]
NANDD_DDRA[15]
NANDD_DDRA[15]
PWRON
PWRON
USB_DM
USB_DP
VUSB_LDO_4V9
P
M
A
R_
XT
_F
R
RF_HB_TX
RF_LB_TX
SIM_DATA
SIM_CLK
RF_HB_RXN
RF_LB_RXN
RF_LB_RXP
RF_TX_EN
RF_2G_BS
HS_MIC_P
BAT_TEMP
T
U
O
_
M
C
P
_
T
B
N
I
_
M
C
P
_
T
B
I2C_SDA
I2C_SCL
S
R
_
D
C
L
K
L
C
M
_
M
A
C
K
L
C
P
_
M
A
C
]
7
[
A
T
A
D
_
M
A
C
]
6
[
A
T
A
D
_
M
A
C
]
5
[
A
T
A
D
_
M
A
C
]
4
[
A
T
A
D
_
M
A
C
]
3
[
A
T
A
D
_
M
A
C
]
2
[
A
T
A
D
_
M
A
C
]
1
[
A
T
A
D
_
M
A
C
]
0
[
A
T
A
D
_
M
A
C
RF_VLOGIC
N
_
T
E
D
_
D
S
M
T
O
O
B
_
F
F_BOOT
BT_UART_RX
BT_UART_TX
P
_
B
I
V
DDR_CAS_N
DDR_CAS_N
DDR_RAS_N
DDR_RAS_N
DDR_CKE
DDR_CKE
DDR_CLK_P
DDR_CLK_P
LDQS
LDQS
DDR_D[15]
DDR_D[15]
DDR_D[05]
DDR_D[05]
DDR_D[01]
DDR_D[01]
DDR_D[02]
DDR_D[02]
DDR_D[00]
DDR_D[00]
DDR_D[14]
DDR_D[14]
DDR_D[13]
DDR_D[13]
DDR_D[11]
DDR_D[11]
DDR_D[10]
DDR_D[10]
DDR_D[09]
DDR_D[09]
DDR_D[07]
DDR_D[07]
DDR_D[06]
DDR_D[06]
DDR_D[04]
DDR_D[04]
DDR_D[03]
DDR_D[03]
NAND_ALE_N
NAND_ALE_N
LDQM
LDQM
UDQM
UDQM
NAND_CLE_N
NAND_CLE_N
DDR_CLK_N
DDR_CLK_N
NAND_DDR_WE_N
NAND_DDR_WE_N
NAND_DDR_WE_N
NAND_BSY_N
NAND_BSY_N
NAND_CS_N
NAND_CS_N
NAND_WP_N
NAND_WP_N
DDR_CS_N
DDR_CS_N
BT_RST_N
NANDD_DDRA[04]
NANDD_DDRA[04]
NANDD_DDRA[04]
MAIN_MIC_N
C
N
Y
S
V
_
M
A
C
N
_
S
C
_
D
C
L
N
_
R
W
_
D
C
L
BT_PCM_CLK
BT_PCM_SYNC
MAIN_MIC_P
C
N
Y
S
V
_
D
C
L
]
2
0
[
D
_
D
C
L
]
4
0
[
D
_
D
C
L
]
6
0
[
D
_
D
C
L
]
7
0
[
D
_
D
C
L
]
5
0
[
D
_
D
C
L
]
3
0
[
D
_
D
C
L
D
I
_
R
E
K
A
M
_
D
C
L
]
0
0
[
D
_
D
C
L
LCD_RST_N
SIM_RST_SELECT
SIM_SELECT
RF_HB_RXP
FM_ANT
BT_CLK_26M
N
_
T
E
S
E
R
RESET_N
JTAG_TRST_N
JTAG_TRST_N
HS_L
JTAG_TDI
JTAG_TDI
JTAG_TMS
JTAG_TMS
JTAG_TCK
JTAG_TCK
JTAG_TDO
JTAG_TDO
BT_CLK_REQ
N
D
W
P
_
M
A
C
K
2
3
_
C
T
R
NANDD_DDRA[00]
NANDD_DDRA[00]
NANDD_DDRA[00]
NANDD_DDRA[01]
NANDD_DDRA[01]
NANDD_DDRA[01]
NANDD_DDRA[02]
NANDD_DDRA[02]
NANDD_DDRA[02]
NANDD_DDRA[03]
NANDD_DDRA[03]
NANDD_DDRA[03]
NANDD_DDRA[05]
NANDD_DDRA[05]
NANDD_DDRA[05]
NANDD_DDRA[06]
NANDD_DDRA[06]
NANDD_DDRA[06]
NANDD_DDRA[07]
NANDD_DDRA[07]
NANDD_DDRA[07]
NANDD_DDRA[08]
NANDD_DDRA[08]
NANDD_DDRA[08]
NANDD_DDRA[09]
NANDD_DDRA[09]
NANDD_DDRA[09]
DDR_D[08]
DDR_D[08]
DDR_D[12]
DDR_D[12]
]
1
0
[
D
_
D
C
L
C
N
Y
S
H
_
M
A
C
HS_MIC_N
HS_R
RCV_SPK_N
RCV_SPK_P
UDQS
UDQS
]
0
[
T
U
O
_
Y
E
K
]
1
[
T
U
O
_
Y
E
K
]
2
[
T
U
O
_
Y
E
K
N
_
T
S
R
_
M
A
C
P
U
E
K
A
W
_
T
B
SIM_RST
MSD_CLK
MSD_D[2]
MSD_CMD
MSD_D[3]
MSD_D[0]
MSD_D[1]
HS_JACK_DET
T
E
D
_
K
O
O
H
_
S
H
NAND_RD_N
NAND_RD_N
T
N
I
_
B
B
D
_
T
B
]
4
[
N
I
_
Y
E
K
]
3
[
N
I
_
Y
E
K
]
2
[
N
I
_
Y
E
K
]
1
[
N
I
_
Y
E
K
N
_
T
N
I
_
B
B
A
]
0
[
N
I
_
Y
E
K
]
3
[
T
U
O
_
Y
E
K
KEY_BL_EN
INDICATOR_1
INDICATOR_2
Hynix 1G NAND/512M DDR
UART PORT
BACK UP Capacitor
NEAR DBB
No SR Open
VDDP_EBU
VDDP_DIG1
VDDP_DIG1
1
GI
D_
P
D
D
V
1
GI
D_
P
D
D
V
7T
NI
E
VDDP_DIG2
RF
VDDP_ULPI
RF
ABB
CC1CC6IO
EINT2
EINT3
VDDP_DIG1
EINT4/EINT1
CC0CC7IO
CC0CC1IO
RF
VDDP_DIG1
VDDP_MMC
VDDP_SIM
5T
NI
E
OI
4
C
C1
C
C
OI
4
C
C0
C
C
OI
0
C
C1
C
C
1T
NI
E
0T
NI
E
VDDP_DIG1
6T
NI
E
OI
3
C
C1
C
C
VDDP_DIG1
4T
NI
E
CT
R_
D
D
V
0T
NI
E
0T
NI
E
6T
NI
E
1T
NI
E
VDDP_DIG1
ABB
VDDP_EBU
ON BOARD ARM9 JTAG & ETM INTERFACE
(FOR SW DEBUGGING / NOT MOUNTED)
ON BOARD UART/USB INTERFACE
Connect GND plane directly
IFX_XMM215x_NAND
(1%)
(10V)
PIN_H12
Seperate and shield
Speaker Supply
(10V)
VDD_IO2
VBATSP
VDD1V8CP
VDD_IO1
PIN_H15
PIN_B16
RF SUPPLIES (DIRTY GND)
PMU SUPPLIES
PIN K10
PIN M11
PIN L9
PIN P10
RF SUPPLIES (CLEAN GND)
(10V)
VBAT_PMU
PIN P16
PIN P18
PIN P12
PIN F6,P6
PIN G11
PIN_B14
PIN_E13
PIN_G16
PIN_G15
ABB SUPPLIES
DBB SUPPLIES
PIN K9
PIN N10
VDD_EBU
PIN L12
7. CIRCUIT DIAGRAM