LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
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3.8.6. MSM6280 microprocessor subsystem
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Industry standard ARM926EJ-S embedded microprocessor subsystem
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16 kB instruction and 16 kB data cache
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Instruction set compatible with ARM7TDMI®
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ARM version 5TEJ instructions
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Higher performance 5 stage pipeline, Harvard cached architecture
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Higher internal CPU clock rate with on-chip cache
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Java hardware acceleration
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Enhanced memory support
Please note that NOR/PSRAM will not be supported on MSM6280.
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75 MHz and 90 MHz bus clock for SDRAM
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32-bit SDRAM
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Dual memory buses separating the high-speed memory subsystem (EBI1) from low-speed
peripherals (EBI2) such as LCD panels
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1.8 V or 2.6 V memory interface support (excluding EBI1)
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NAND FLASH memory interface
- 8/16-bit data I/O width NAND flash support
- 1- or 4-bit ECC
- 512-byte/2KB page-size support
- 2 chip selects supported for NAND Flash
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Boot from NAND
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Low-power SDRAM (LP-SDRAM) interface
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Internal watchdog and sleep timers
3.8.7. Supported interface features
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USB On-the-Go core supports both slave and host functionality
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Three universal asynchronous receiver transmitter (UART) serial ports
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USIM controller (via UART)
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Integrated 4-bit secure digital (SD) controller for SD and Mini SD cards
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Parallel LCD interface
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General-purpose I/O pins
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External keypad interface
