3. H/W Circuit Description
- 38 -
3.4. Camera Circuit
General description of CLC344ED Camera chipset.
- External Clock Source Up to 27 MHz
- Internal Clock Divider 1/2, 1/3, 1/4 for Sensor Clock Output
- Support Standard SRAM Interface (6bit Address & 16bit Data) for CPU Interface
- 4Mbit Stacked SRAM
- Support LCD Signal By-pass Mode
- Fully Hardwired JPEG and Motion-JPEG Codec
- Support three General Port IO
- 8 x 8 100pin BGA Package
The camera IC, CLC344ED, is controlled through _RD, _WR, CAM_HOLD, LCD_RESET, A[1-6],
DATA[0-15] by CALYPSO. In by-pass mode, CLC344ED bypasses all LCD control signal from
CALYPSO to LCD module. In operating mode, CLC344ED samples the image data from camera
sensor connected on CN2 through C_CD[0-7], C_MCLK, C_PCLK, C_HS, C_VS, C_SDA, C_SCK,
C_RST signals and controls the LCD module.
The camera power is provided by U602 ADP3330. It converts VBAT from battery to 2.85V
Figure 21. CLC344ED, Camera Chip Block Diagram
Summary of Contents for L1150
Page 1: ...Service Manual Model L1150 Service Manual L1150 P N MMBD0034601 Date June 2004 Issue 1 0 ...
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