LG L1150, Service Manual

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3. H/W Circuit Description
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3.1.2. Receiver Part
The Aero I transceiver uses a low-IF receiver architecture which allows for the on-chip integration of
the channel selection filters, eliminating the external RF image reject filters and the IF SAW filter
required in conventional superheterodyne architectures. Compared to a direct-conversion architecture,
the low-IF architecture has a much greater degree of immunity to dc offsets, which can arise from RF
local oscillator (RFLO) self-mixing, nd-order distortion of blockers, and device 1/f noise. This relaxes
the common-mode balance requirements on the input SAW filters, and simplifies PC board design and
manufacturing. Three differential-input LNAs are integrated. The GSM input supports the GSM 850
(869 ~ 894 MHz). The DCS input supports the DCS 1800 (1805 ~ 1880 MHz) band. The PCS input
supports the PCS 1900 (1930 ~ 1990 MHz) band. For quad-band designs, SAW filters for the GSM
850 band should be connected to a balanced combiner which drives the GSM input for both bands.
For dual-band designs using the Si4205DB, the DCS input should be used for either DCS 1800 or
PCS 1900 bands. The LNA inputs are matched to the 150
Ω balancedoutput SAW filters through
external LC matching networks. The LNA gain is controlled with the LNAG[1:0] and LNAC[1:0] bits in
register 05h. A quadrature image-reject mixer downconverts the RF signal to a 100 kHz intermediate
frequency (IF) with the RFLO from the frequency synthesizer. The RFLO frequency is between 1737.8
to 1989.9 MHz, and is internally divided by 2 for GSM 850 mode. The mixer output is amplified with an
analog programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register
05h. The quadrature IF signal is digitized with high resolution A/D converters ADCs). The ADC output
is downconverted to baseband with a digital 100 kHz quadrature LO signal. Digital decimation and IIR
filters perform channel selection to remove blocking and reference interference signals. The response
of the IIR filter is programmable to a high selectivity setting (CSEL = 0) or a low selectivity setting
(CSEL = 1). The low selectivity filter has a flatter group delay response which may be desirable where
the final channelization filter is in the baseband chip. After channel selection, the digital output is
scaled with a digital PGA, which is controlled with the DGAIN[5:0] bits in register 05h. The LNAG[1:0],
LNAC[1:0], AGAIN[2:0] and DGAIN[5:0] bits must be set to provide a constant amplitude signal to the
baseband receive inputs. See “AN51: Aero Transceiver AGC Strategy” for more details.
DACs drive a differential analog signal onto the RXIP, RXIN, RXQP, and RXQN pins to interface to
standard analog-input baseband ICs. No special processing is required in the baseband for offset
compensation or extended dynamic range. The receive and transmit baseband I/Q pins can be
multiplexed together into a 4- wire interface. The common mode level at the receive I and Q outputs is
programmable with the DACCM[1:0] bits, and the full scale level is programmable with the DACFS[1:0]
bits in register 12h.