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3. Technical Brief
LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
B. CPU Subsystem
•
Access CPU subsystem
The digital baseband controller includes an access CPU subsystem, which includes the submodules
described below.
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32 KiB I-cache
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16 KiB D-cache
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Page table
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Memory Management Unit (MMU)
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JTAG
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ETM9
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26 KiB I-TCM
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8 KiB D-TCM
•
Application CPU subsystem
The digital baseband controller includes an Application CPU subsystem, which includes the
submodules described below.
−
32 KiB I-cache
−
16 KiB D-cache
−
Page table
−
MMU
−
JTAG
−
ETM9
−
8 KiB I-TCM
−
8 KiB D-TCM
C. Peripheral Hardware Subsystem
The digital baseband controller includes hardware that supports mobile terminal peripherals such as a
MMC, SD, UART, I2C, USB, keypad, and infrared. Collectively, this hardware comprises the
Peripheral subsystem.
The functional blocks of the Peripheral subsystem connect to the peripheral bus through four separate
bridges, which provide a simple interface to support different timing and memory access
arrangements.
D. DSP Hardware Subsystem
The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which contains the DSP
CPU together with a tightly coupled memory. The DSP is the Ceva-X 1620 core with a 64 kB
instruction RAM and a 64 kB data RAM. It also contains debug logic and interfaces. In addition to the
megacell, the DSPSUB includes external memories, peripheral units, and interfaces. The DSP
megacell is clocked at 208 MHz.
The DSPSUB includes an AHB master and an AHB slave interface. The AHB master provides a direct
access to the Internal Random Access Memory (IRAM) in the EGG core through the AHB. The AHB
slave interface allows the CPU and the DMA to access in the program and data RAM residing in the
DSPSUB.
