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3. TECHNICAL BRIEF
3.3 Subsystem(MSM7227)
3.3.1 Architecture and baseband processing features
High-performance ARM1136JF-S 600 MHz application processor:
- ARM® architecture v6
- 32 kB instruction and 32 kB data cache
- 256 kB ARM11™ L2 cache
- 4 kB level-one tightly-coupled memory (TCM)
- 8-stage pipeline, branch prediction with return stack
- Supports the ARM and Thumb instruction sets, and Jazelle™ technology to enable direct
- execution of Java byte-codes
- Low-interrupt latency
Industry standard ARM926EJ-S 400 MHz embedded microprocessor subsystem
- 16 kB instruction and 16 kB data cache
- ARM version 5TEJ instructions
- Higher-performance five-stage pipeline, Harvard cached architecture
- Higher internal CPU clock rate with on-chip cache
- Internal watchdog and sleep timers
QDSP5000 320 MHz application digital signal processing (ADSP)
- 512 kB L2 cache
QDSP4000 122.88 MHz modem digital signal processing (MDSP)
3.3.2 Memory support features
256 kB internal memory (IMEM) for graphics, internal functions, DSP, etc.
Dual-memory buses separating the high-speed memory subsystem (EBI1) from low-speed peripherals
(EBI2) such as LCD panels
Enhanced EBI1 memory support: 200 MHz bus clock for DDR SDRAM
EBI2 support:
- 1.8 or 2.6 V memory interface support
- NAND/OneNAND™ flash memory interface
- Boot from NAND/OneNAND
- LCD and Universal Broadcast Modem™ (UBM™) support
3. Technical Brief