- 20 -
LGE Internal Use Only
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
3.3. Digital Baseband
<Fig.6> OMAPV1030 Block Diagram
3.3.1 General description
The OMAPV1030 E-GPRS multimedia device belongs to the Texas Instruments OMAP-Vox_ processors family. It
combines both a modem engine and an application engine. Memory and CPU resources are shared
between modem and application processing.
The OMAPV1030 chip is based on the OMAP3.4 architecture and integrates two processor subsystems:
- An MPU subsystem based on an ARM926EJ-S
- A DSP subsystem based on a UMA 2.6 architecture integrating a C55x DSP core
The OMAPV1030’s silicon process technology is a c027.0 90-nm digital CMOS.
Boot ROM
Secure eFuse
Secure RAM
Security layer
SDRAM Flash and
SRAM
Internal SRAM
Camera core
Enhanced LCD
OCP-I
OCP-T2
OCP-T1
EMIFS
EMIFF
Traffic controller
DSP MMU
DSP
subsystem
MPUI
DSP private
peripherals
Timers (x3)
WD timer
DSP DMA handler
DSP interrupt
handler
Static switches
APLL
ULPDR
MPU/DSP shared peripherals
Dynamic switches
OCP static switches
TIPB static switches
32k Sync timer
Frame counter
GPIO (x2)
GP timer (x2)
Serial radio IF
McBSP1
McBSP RF
MMC/SDIO2
Nand flash ctrl
SPI
UART (x3)
I C(x2)
2
ULPDR
CIPHER A5
TPU
TSP
GEA 1/2/3
USIM
MCSI (x2)
USB controller
Host
Device
OTG
LCD
controller
MPU
subsystem
System
DMA
controller
TIPB bridge (x2)
Test:
E2TLM, BCM, SCM,DielD
JTAG, FuseFarm
MPU public peripherals
uWire
HDQ/1-Wire
MMC/SDIO1
Keyboard controller
Memory stick
OMAPV1030 OS timer
LPG (x2)
PWT
MPU private peripherals
Timers (x3)
WD timers
System DMA handler
MPU level 2 INTH
Secure watchdog
32k watchdog
OMAPV1030 config.
SHA1/MDS5
AES
PKA
LCDCONV
RNG
DES/3DES
OMAPV1030 EDGE multimedia platform