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Only for training and service purposes
LGE Internal Use Only
ES8391 Pin Description
Table 1 lists the pin descriptions for the ES8391.
Table 1 ES8391 Pin Description
Names
Pin Numbers
I/O
Definitions
VD33
1, 14, 30, 46, 62,
77, 95, 119, 133,
186, 203
P
I/O power supply.
VS33
2, 15, 29, 47, 61,
78, 94, 120, 132,
187, 204
G
Ground.
DCS1#
3
O
DRAM chip select 1 (active-low).
DCS0#
4
O
DRAM chip select 0 (active-low).
DRAS0#
5
I/O
DRAM row address strobes (active-low).
SEL_PLL2
I
Strap pin: System and DSCK output clock frequency selection is made at the
rising edge of RESET#. The matrix below lists the available PLL bit settings.
Strapped to VD33PLL or VS33PLL via 4.7-k
Ω
resistor; read-only during reset.
SEL_PLL3
6
I
Clock source select: Strapped to VD33PLL or VS33PLL via 4.7-k! resistor; read
only during reset.
DCAS#
O
DRAM column address strobe (active-low).
SEL_PLL0
7
I
Strap pin. Refer to the description and matrix for SEL_PLL2, pin 5.
DOE#
O
DRAM output enable (active-low).
DWE#
8
O
DRAM write enable (active-low).
SEL_PLL1
Strap pin. Refer to the description and matrix for SEL_PLL2, pin 5.
DSCK
9
O
Output clock to DRAM.
DQM
10
O
Data input/output mask.
DB[15:0]
31, 28-22, 11-13,
17-21
I/O
DRAM data bus.
VDD
16, 48, 79, 124, 188
P
Core power supply.
AUX2[6-0]
200, 191, 138, 93,
70, 41, 32
I/O
Aux2 data I/O 6-0.
SEL_PLL2
SEL_PLL1
SEL_PLL0
Clock Type (MHz)
0
0
0
Bypass
0
0
1
121.5MHz
0
1
0
128.25MHz
0
1
1
135MHz
1
0
0
141.75MHz
1
0
1
155.25MHz
1
1
0
162MHz
1
1
1
148.5MHz
SEL_PLL3
Clock Source
1
Crystal oscillator
0
CLK input
I
2) PIN DESCRIPTIONS
