LG F7100, Service Manual

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3. TECHNICAL BRIEF
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signals are automatically swapped when switching bands. Additionally, the SWAP bit in register 03h
can be used to manually exchange the I and Q signals.
Low-pass filters before the OPLL phase detector reduce the harmonic content of the quadrature
modulator and feedback mixer outputs. The cutoff frequency of the filters is programmable with the
FIF[3:0] bits in register 04h (Figure 3-3), and should be set to the recommended settings detailed in
the register description.
(3) Frequency Synthesizer
The Aero I transceiver integrates two complete PLLs including VCOs, varactors, resonators, loop
filters, reference and VCO dividers, and phase detectors. The RF PLL uses two multiplexed VCOs.
The RF1 VCO is used for receive mode, and the RF2 VCO is used for transmit mode. The IF PLL is
used only during transmit mode. All VCO tuning inductors are also integrated. The IF and RF output
frequencies are set by programming the N-Divider registers, NRF1, NRF2 and NIF. Programming the
N-Divider register for either RF1 or RF2 automatically selects the proper VCO. The output frequency of
each PLL is as follows:
fout = N x f•ı
The DIV2 bit in register 31h controls a programmable divider at the XIN pin to allow either a 13 or 26
MHz reference frequency. For receive mode, the RF1 PLL phase detector update rate (f•
ı ) should be
programmed f• ı = 100 kHz for DCS 1800 or PCS 1900 bands, and f• ı = 200 kHz for GSM 850 and E-
GSM 900 bands. For transmit mode, the RF2 and IF PLL phase detector update rates are always
f•
ı =200 kHz.
Figure 3-4 Block Diagram of Frequency Synthesizer part of SI4205