LG EA71G, Service Manual

Page: 33 / 95

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M0_DDR_DM1
+1.5V_DDR
M0_DDR_VREFCA
M0_1_DDR_VREFDQ
M0_DDR_WEN
M0_DDR_DQ31
M0_DDR_A3
M1_DDR_RESET_N
C414
0.1uF
H5TQ4G63CFR-TEC
IC402
MAIN_SK_HYNIX_DDR
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
+1.5V_DDR
M0_DDR_DQ19
M0_DDR_A12
+1.5V_DDR
M0_DDR_RESET_N
M0_DDR_VREFDQ
M1_CS1_N
M0_DDR_DQ14
M0_DDR_A5
M1_DDR_WEN
M0_DDR_WEN
H5TQ4G63CFR-TEC
IC400
MAIN_SK_HYNIX_DDR
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
R433
1K
1%
M1_DDR_ODT
M1_DDR_DQS2
M1_DDR_CASN
M0_DDR_CASN
M0_DDR_DQ20
R449
120
1%
M0_DDR_DQ26
M0_CLK
M1_DDR_DQ7
M0_DDR_BA2
C441 0.1uF
16V
+1.5V_DDR
M1_DDR_RASN
M1_DDR_DQS_N3
R441 240
R407
1K
1%
M0_DDR_DQS2
M1_DDR_DQS_N0
M0_DDR_DQ11
M0_DDR_A2
M1_DDR_DQ15
M1_1_DDR_VREFDQ
C439 0.1uF
16V
M1_DDR_A12
M0_CLKN
M0_CLKN
M1_DDR_DQS_N2
M0_DDR_DQ13
M0_DDR_A10
M0_CS0_N
M0_DDR_DQ1
M0_DDR_BA2
M1_DDR_DQ6
M1_DDR_BA2
M1_DDR_A1
M0_DDR_DQS_N0
M0_CLK
M1_DDR_DQS1
+1.5V_DDR
M0_DDR_A9
C431
0.1uF
16V
M0_DDR_DQ3
M0_DDR_A0
M1_DDR_DQ13
M0_DDR_DQS3
M1_DDR_A2
M1_CLKN
M1_DDR_DQS3
C416
0.1uF
C409
0.1uF
16V
M1_DDR_DQ26
M0_DDR_A13
M0_DDR_DQ15
M0_DDR_A4
M1_DDR_DQ12
M0_DDR_A11
C440 0.1uF
16V
M1_DDR_A6
M0_DDR_DQ6
C400
0.1uF
16V
M1_DDR_DQS_N1
M1_DDR_DQS_N1
M0_DDR_A6
M1_CLK
M0_DDR_DQ20
M0_DDR_A6
M1_DDR_DQ0
M1_DDR_A13
C438 0.1uF
16V
M1_DDR_A8
M0_DDR_RASN
C402
0.1uF
16V
M1_DDR_DQS_N0
M0_DDR_DQS_N1
M1_DDR_DQ21
M0_DDR_BA0
C430
0.1uF
16V
M0_DDR_DQ18
M0_DDR_BA0
M1_DDR_DQ2
M1_DDR_DQ18
M1_DDR_A14
M1_DDR_DQ0
M0_DDR_DQ26
C401
0.1uF
16V
M1_DDR_DQS0
M1_DDR_DQ16
M1_CLKN
R408
1K
1%
M0_DDR_DQS_N2
M0_DDR_DQ29
M0_DDR_A7
M1_DDR_DQ14
M0_DDR_DQ8
M0_DDR_A2
M1_CS0_N
C403
0.1uF
16V
M1_DDR_DM2
+1.5V_DDR
+1.5V_DDR
R425
1K
1%
M0_DDR_A0
M0_DDR_CASN
M0_DDR_DQ5
M0_DDR_ODT
M1_DDR_DQ11
M0_CLK
M1_DDR_A4_1
M1_DDR_DQS2
C421
0.1uF
16V
M1_DDR_DM3
M1_DDR_DQ24
C426
0.1uF
16V
M0_1_DDR_VREFDQ
M0_DDR_DQ10
M1_DDR_A14
M0_DDR_DQ8
M0_DDR_CASN
M1_DDR_DQ3
M1_DDR_A2
R445 240
M1_DDR_DQS1
C423
0.1uF
16V
M1_DDR_DM0
M1_1_DDR_VREFCA
R428
1K
1%
M1_DDR_RASN
M0_DDR_DQ19
M1_DDR_DQ1
M1_DDR_A8
M0_DDR_A7
M0_DDR_A5_1
C420
0.1uF
16V
M1_DDR_DM1
M0_DDR_DQS_N3
C424
0.1uF
16V
M0_DDR_DQ23
M1_DDR_DQ14
M0_DDR_DQ7
M1_DDR_DQ9
M0_DDR_A1
M0_DDR_A12
M1_DDR_DQ9
C422
0.1uF
16V
M1_DDR_VREFDQ
C425
0.1uF
16V
C406
0.1uF
16V
M0_DDR_DQ1
M0_CS1_N
M0_DDR_DQ17
M1_DDR_DQ4
+1.5V_DDR
M1_DDR_DQ19
M1_DDR_DQ11
M1_DDR_A9
C418 0.1uF 16V
R401 240
1%
OPT
M1_DDR_A9
M1_DDR_DQ13
C429
0.1uF
16V
R410
1K
1%
+1.5V_DDR
M1_DDR_A7
M0_DDR_DQ22
M1_DDR_DQ10
M0_DDR_BA0
R443
240
1%
M1_DDR_BA0
M1_DDR_DQ3
C419 0.1uF 16V
VREF_M0
M1_DDR_CASN
M1_DDR_A10
C428
0.1uF
16V
M1_CLKN
C410 0.1uF
M0_DDR_DQ16
M1_DDR_DQ8
M0_DDR_VREFDQ
M1_CLK
M1_DDR_DQ15
C413
0.1uF
M0_DDR_A0
M0_CS1_N
M0_DDR_A2
M1_DDR_DQ5
C427
0.1uF
16V
M1_DDR_A0
M1_DDR_A14
M0_DDR_DQ30
M1_DDR_DQ5
C408
0.1uF
16V
M0_DDR_DQ18
M1_DDR_DQS_N2
M1_DDR_A6
M0_DDR_A10
M1_CS1_N
R402
1K
1%
M0_DDR_A8
R429
1K
1%
M1_DDR_DM2
M0_DDR_DQ10
M1_DDR_DQ24
M0_DDR_A1
M1_DDR_A7
R437
1K
M0_DDR_DQ16
M0_DDR_A4_1
R403
1K
1%
M1_DDR_DQ23
+1.5V_DDR
M0_DDR_DQ4
M0_DDR_DQS_N2
M1_DDR_DQ27
M1_DDR_A3
M1_DDR_BA2
M1_DDR_DM3
M1_DDR_A0
M0_DDR_A5_1
+1.5V_DDR
M1_CLK
+1.5V_DDR
M1_DDR_WEN
M0_DDR_DQS0
M1_DDR_DQ16
M0_DDR_DQ2
M1_DDR_DQ8
M0_DDR_DQ31
M1_DDR_DQ7
M1_DDR_A4_1
R405
1K
1%
M1_DDR_DQ4
+1.5V_DDR
M1_DDR_A3
M0_DDR_DQS_N3
M1_DDR_DQ17
M0_DDR_CKE
M0_DDR_DQ0
M1_DDR_DQ28
M1_DDR_A6
M0_CLKN
M1_DDR_A5_1
VREF_M1
C412
0.1uF R436
1K
M0_DDR_DQS_N0
M1_DDR_DQ19
R409
1K
1%
M1_DDR_DQ31
M0_DDR_A11
M1_CS1_N
M0_DDR_DM3
M1_CS0_N
R404
1K
1%
M1_DDR_A1
C433
0.1uF
16V
M1_DDR_VREFCA
+1.5V_DDR
M0_DDR_DQS2
M1_DDR_DQ29
R426
1K
+1.5V_DDR
M0_DDR_DQ17
M1_DDR_WEN
M0_DDR_A6
M0_CS0_N
+1.5V_DDR
M1_DDR_A10
M0_DDR_BA1
C435
0.1uF
16V
M1_DDR_CKE
M0_DDR_DQS3
M1_DDR_DQ20
M0_1_DDR_VREFCA
M1_DDR_A1
M0_DDR_RESET_N
M1_DDR_DQS3
M0_DDR_DQ30
M0_CS1_N
M0_DDR_A9
M1_DDR_A5
M0_DDR_DQ22
C437
0.1uF
16V
R415
1K
1%
M0_DDR_DQS_N1
M1_DDR_DQ23
M0_DDR_A9
M0_DDR_A7
M1_DDR_BA1
M0_DDR_DQ3
M0_CS0_N
M0_DDR_A8
+1.5V_DDR
M1_DDR_A4
M0_DDR_A13
+1.5V_DDR
R413
1K
1%
M0_DDR_DQS1
M1_DDR_DQ31
M1_DDR_DQ1
M0_DDR_CKE
C417
0.1uF
M0_DDR_DQ14
M0_CS1_N
M0_DDR_BA1
VREF_M1
M1_DDR_A9
C411 0.1uF
R434
1K
1%
M0_DDR_DM3
M1_DDR_DQ25
M1_DDR_RESET_N
M0_DDR_A14
M1_DDR_CKE
M1_DDR_DQ6
M0_DDR_DQS1
R446
120
1%
M0_DDR_DQ6
M1_CLKN
M1_DDR_A11
M1_DDR_DM1
M0_DDR_DM0
M1_DDR_DQ22
M1_DDR_A11
M0_DDR_DQ27
M1_DDR_A4
M0_DDR_A14
M0_DDR_DQ28
R447
120
1%
M0_DDR_DQ25
M0_DDR_A13
M1_DDR_A3
M1_DDR_ODT
R435
1K
M0_DDR_DM1
M1_DDR_DQ18
M1_DDR_RESET_N
M1_DDR_A12
M0_DDR_DQ7
M1_DDR_DQ30
M1_DDR_DQ12
R451
120
1%
M0_DDR_DQ13
M0_DDR_RASN
M1_DDR_A0
M1_DDR_DQ22
M0_DDR_DM2
M1_DDR_DQ26
M0_DDR_A3
M1_DDR_A5
+1.5V_DDR
M1_DDR_A11
R450
120
1%
M0_DDR_DQ28
M0_DDR_A11
M1_DDR_A7
M0_DDR_DQ11
M1_DDR_VREFDQ
VREF_M0
M1_DDR_DQ21
M1_DDR_A10
M0_DDR_DQ29
M1_DDR_DQ29
M1_DDR_BA0
M0_DDR_DQ12
+1.5V_DDR_INSTANTBOOT
M0_DDR_DQ4
M0_CS0_N
M1_DDR_A13
M0_DDR_ODT
R412
1K
1%
R400 240
1%
OPT
M1_DDR_DQ28
M0_DDR_DQ21
M0_DDR_BA1
M0_DDR_A3
M0_DDR_ODT
M0_DDR_VREFCA
M0_DDR_DQ27
M0_DDR_A14
M1_DDR_BA2
+1.5V_DDR
R432
1K
1%
M1_DDR_DQ30
M0_DDR_DQS0
M1_DDR_DQ25
M0_DDR_DQ15
M0_DDR_A4
M1_DDR_DQ17
R453
120
1%
M0_DDR_DQ12
M0_DDR_A12
M1_DDR_BA0
M1_DDR_DQ20
R422
0
OPT
R431
1K
1%
+1.5V_DDR
M0_DDR_DQ9
M1_DDR_A12
M0_DDR_DQ5
M1_DDR_CKE
M0_DDR_BA2
M1_CS0_N
M0_DDR_DQ23
M0_DDR_CKE
M1_DDR_BA1
M1_DDR_A13
R423 0
OPT
+1.5V_DDR
M1_DDR_DQS0
M1_DDR_DQ2
M0_DDR_DQ24
M1_DDR_A8
M0_DDR_DM2
R452
120
1%
M0_DDR_DQ0
M0_DDR_RESET_N
M1_DDR_CASN
M0_CLK
+1.5V_DDR
M1_1_DDR_VREFCA
R439
240
1%
M0_DDR_A4_1
C415
0.1uF
M1_DDR_VREFCA
M1_CS1_N
M0_DDR_DQ21
M0_DDR_A10
M1_DDR_CKE
R430 0
OPT
R414
1K
1%
M1_DDR_BA1
M1_DDR_A2
M0_1_DDR_VREFCA
M0_DDR_A5
M1_CS0_N
M0_DDR_DQ9
M0_CLKN
M1_CLK
M1_DDR_DQ10
R427
0
OPT
M0_DDR_A8
M0_DDR_DQ25
M1_DDR_A5_1
+1.5V_DDR_INSTANTBOOT
M0_DDR_DQ2
M0_DDR_A1
M1_DDR_ODT
M1_DDR_DQ27
H5TQ4G63CFR-TEC
IC401
MAIN_SK_HYNIX_DDR
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_1_DDR_VREFDQ
M0_DDR_RASN
M0_DDR_DM0
R424
1K
1%
M1_DDR_DQS_N3
M1_DDR_DM0
R448
120
1%
M0_DDR_DQ24
M0_DDR_WEN
M1_DDR_RASN
M0_DDR_CKE
C436
0.1uF
16V
C442
0.1uF
16V
C432
0.1uF
16V
+1.5V_DDR
+1.5V_DDR
C443
0.1uF
16V C445
0.1uF
16V C434
0.1uF
16V
C405
0.1uF
16V
C446
0.1uF
16V
C404
0.1uF
16V C407
0.1uF
16V
C444
0.1uF
16V C447
10uF
10V C448
10uF
10V C449
10uF
10V
C450
10uF
10V C451
10uF
10V C452
10uF
10V
R420
27
R421
27
R418
27
R419
27
C457
10uF
10V C455
10uF
10V C453
10uF
10V
C458
10uF
10V C456
10uF
10V C454
10uF
10V
C459
10uF
10V
C460
10uF
10V
IC100
LGE6551_AA1
DC1_A0_PAR_1
E35
DC1_A1_A3
F38
DC1_A2_BA0
C37
DC1_A3_WE_N/A14
B34
DC1_A4_A13
H34
DC1_A4_EXT_A1
G36
DC1_A5_A6
D35
DC1_A5_EXT_A0
C34
DC1_A6_RAS_N/A16
G34
DC1_A7_A8
D34
DC1_A8_ODT
G35
DC1_A9_A2
D38
DC1_A10_A5
K35
DC1_A11_A4
F34
DC1_A12_A9
H35
DC1_A13_A11
D37
DC1_A14_A12/BC_N
F37
DC1_A15_BA1
H37
DC1_BA0_BG0_1
B35
DC1_BA1_A7
G37
DC1_BA2_A4_1
E34
DC1_CASN_ACT_N
E37
DC1_CKE_A5_1
J35
DC1_CLK_CLK
J37
DC1_CLKB_CLKB
J36
DC1_CSN_1_CSN_1
AA33
DC1_CSN_CSN
L34
DC1_ODT_X
B37
DC1_RASN_PAR
F35
DC1_RST_RST
C36
DC1_WEN_A10/AP
E36
DC1_X_ALERT
K34
DC1_X_ALERT_1
J34
DC1_X_BG0
C35
DC1_X_CASN/A15
L35
DC1_X_CKE
A36
DC1_X_TEN
H38
DC1_DQ0_DQ0
R38
DC1_DQ1_DQ1
M36
DC1_DQ2_DQ6
R37
DC1_DQ3_DQ3
N37
DC1_DQ4_DQ4
P36
DC1_DQ5_DQ5
M37
DC1_DQ6_DQ2
P37
DC1_DQ7_DQ7
N38
DC1_DQ8_DQ13
M35
DC1_DQ9_DQ12
T35
DC1_DQ10_DQ15
M34
DC1_DQ11_DQ14
T34
DC1_DQ12_DQ9
N34
DC1_DQ13_DQ10
R34
DC1_DQ14_DQ11
N35
DC1_DQ15_DQ8
R35
DC1_DQ16_DQ16
AA38
DC1_DQ17_DQ17
V36
DC1_DQ18_DQ22
AA37
DC1_DQ19_DQ19
W37
DC1_DQ20_DQ20
Y36
DC1_DQ21_DQ21
V37
DC1_DQ22_DQ18
Y37
DC1_DQ23_DQ23
W38
DC1_DQ24_DQ29
V35
DC1_DQ25_DQ28
AB35
DC1_DQ26_DQ31
V34
DC1_DQ27_DQ30
AB34
DC1_DQ28_DQ25
W34
DC1_DQ29_DQ26
AA34
DC1_DQ30_DQ27
W35
DC1_DQ31_DQ24
AA35
DC1_DQS0_DQS0
T37
DC1_DQS0B_DQS0B
T36
DC1_DQS1_DQS1
P34
DC1_DQS1B_DQS1B
P35
DC1_DQS2_DQS2
AB37
DC1_DQS2B_DQS2B
AB36
DC1_DQS3_DQS3
Y34
DC1_DQS3B_DQS3B
Y35
DC1_DM0_DM0_N/DBIL_N
L37
DC1_DM1_DM1_N/DBIU_N
T33
DC1_DM2_DM2_N/DBIL_N
U37
DC1_DM3_DM3_N/DBIU_N
AB33
DC1_ZQ_ZQ
A35
DC1_VREF_VREF
A37
DC1_1V5_1
R26
DC1_1V5_2
T26
DC1_1V5_3
U26
DC1_1V5_4
V26
DC1_1V5_5
W26
DC1_1V5_6
Y26
DC1_1V5_7
AA26
DC1_1V5_8
A32
DC1_1V5_9
B32
DC1_1V5_10
C32
DC1_1V5_11
D32
DC1_1V5_12
E32
DC1_1V5_13
F32
DC2_A0_PAR_1
D12
DC2_A1_A3
A13
DC2_A2_BA0
B10
DC2_A3_WE_N/A14
E9
DC2_A4_A13
E15
DC2_A4_EXT_A1
C14
DC2_A5_A6
D11
DC2_A5_EXT_A0
E10
DC2_A6_RAS_N/A16
E14
DC2_A7_A8
E11
DC2_A8_ODT
D14
DC2_A9_A2
A11
DC2_A10_A5
D17
DC2_A11_A4
E13
DC2_A12_A9
D15
DC2_A13_A11
B11
DC2_A14_A12/BC_N
B13
DC2_A15_BA1
B15
DC2_BA0_BG0_1
D9
DC2_BA1_A7
B14
DC2_BA2_A4_1
E12
DC2_CASN_ACT_N
B12
DC2_CKE_A5_1
D16
DC2_CLK_CLK
B16
DC2_CLKB_CLKB
C16
DC2_CSN_1_CSN_1
F28
DC2_CSN_CSN
E18
DC2_ODT_X
B9
DC2_RASN_PAR
D13
DC2_RST_RST
C10
DC2_WEN_A10/AP
C12
DC2_X_ALERT
E17
DC2_X_ALERT_1
E16
DC2_X_BG0
D10
DC2_X_CASN/A15
D18
DC2_X_CKE
F9
DC2_X_TEN
A15
DC2_DQ0_DQ0
A22
DC2_DQ1_DQ1
C19
DC2_DQ2_DQ6
B22
DC2_DQ3_DQ3
B20
DC2_DQ4_DQ4
C21
DC2_DQ5_DQ5
B19
DC2_DQ6_DQ2
B21
DC2_DQ7_DQ7
A20
DC2_DQ8_DQ13
D19
DC2_DQ9_DQ12
D23
DC2_DQ10_DQ15
E19
DC2_DQ11_DQ14
E23
DC2_DQ12_DQ9
E20
DC2_DQ13_DQ10
E22
DC2_DQ14_DQ11
D20
DC2_DQ15_DQ8
D22
DC2_DQ16_DQ16
A28
DC2_DQ17_DQ17
C25
DC2_DQ18_DQ22
B28
DC2_DQ19_DQ19
B26
DC2_DQ20_DQ20
C27
DC2_DQ21_DQ21
B25
DC2_DQ22_DQ18
B27
DC2_DQ23_DQ23
A26
DC2_DQ24_DQ29
D25
DC2_DQ25_DQ28
D29
DC2_DQ26_DQ31
E25
DC2_DQ27_DQ30
E29
DC2_DQ28_DQ25
E26
DC2_DQ29_DQ26
E28
DC2_DQ30_DQ27
D26
DC2_DQ31_DQ24
D28
DC2_DQS0_DQS0
B23
DC2_DQS0B_DQS0B
C23
DC2_DQS1_DQS1
E21
DC2_DQS1B_DQS1B
D21
DC2_DQS2_DQS2
B29
DC2_DQS2B_DQS2B
C29
DC2_DQS3_DQS3
E27
DC2_DQS3B_DQS3B
D27
DC2_DM0_DM0_N/DBIL_N
B18
DC2_DM1_DM1_N/DBIU_N
F23
DC2_DM2_DM2_N/DBIL_N
B24
DC2_DM3_DM3_N/DBIU_N
F29
DC2_ZQ_ZQ
A34
DC2_VREF_VREF
A33
DC2_1V5_1
A31
DC2_1V5_2
B31
DC2_1V5_3
C31
DC2_1V5_4
D31
DC2_1V5_5
E31
DC2_1V5_6
F31
DC2_1V5_7
N20
DC2_1V5_8
N21
DC2_1V5_9
N22
DC2_1V5_10
N23
DC2_1V5_11
N24
DC2_1V5_12
N25
DC2_1V5_13
N26
H5TQ4G63CFR-TEC
IC403
MAIN_SK_HYNIX_DDR
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B4G1646E-BCNB
IC401-*1
SUB_SAMSUNG_DDR
A0
N3
A1 P7
A2 P3
A3 N2
A4
P8
A5 P2
A6 R8
A7 R2
A8
T8
A9 R3
A10/AP L7
A11 R7
A12/BC
N7
A13 T3
NC_5
M7
BA0 M2
BA1 N8
BA2
M3
CK J7
CK K7
CKE
K9
CS L2
ODT K1
RAS
J3
CAS
K3
WE L3
RESET
T2
DQSL F3
DQSL
G3
DQSU C7
DQSU B7
DML
E7
DMU D3
DQL0
E3
DQL1
F7
DQL2 F2
DQL3 F8
DQL4
H3
DQL5
H8
DQL6 G2
DQL7 H7
DQU0
D7
DQU1 C3
DQU2 C8
DQU3
C2
DQU4
A7
DQU5 A2
DQU6 B8
DQU7
A3
VREFCA
M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4
K2
VDD_5 K8
VDD_6 N1
VDD_7
N9
VDD_8
R1
VDD_9 R9
VDDQ_1
A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8
H2
VDDQ_9
H9
NC_1 J1
NC_2
J9
NC_3
L1
NC_4 L9
A14 T7
VSS_1 A9
VSS_2 B3
VSS_3
E1
VSS_4
G8
VSS_5 J2
VSS_6 J8
VSS_7
M1
VSS_8
M9
VSS_9 P1
VSS_10 P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9
G9
K4B4G1646E-BCNB
IC403-*1
SUB_SAMSUNG_DDR
A0
N3
A1 P7
A2 P3
A3 N2
A4
P8
A5 P2
A6 R8
A7 R2
A8
T8
A9 R3
A10/AP L7
A11 R7
A12/BC
N7
A13 T3
NC_5
M7
BA0 M2
BA1 N8
BA2
M3
CK J7
CK K7
CKE
K9
CS L2
ODT K1
RAS
J3
CAS
K3
WE L3
RESET
T2
DQSL F3
DQSL
G3
DQSU C7
DQSU B7
DML
E7
DMU D3
DQL0
E3
DQL1
F7
DQL2 F2
DQL3 F8
DQL4
H3
DQL5
H8
DQL6 G2
DQL7 H7
DQU0
D7
DQU1 C3
DQU2 C8
DQU3
C2
DQU4
A7
DQU5 A2
DQU6 B8
DQU7
A3
VREFCA
M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4
K2
VDD_5 K8
VDD_6 N1
VDD_7
N9
VDD_8
R1
VDD_9 R9
VDDQ_1
A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8
H2
VDDQ_9
H9
NC_1 J1
NC_2
J9
NC_3
L1
NC_4 L9
A14 T7
VSS_1 A9
VSS_2 B3
VSS_3
E1
VSS_4
G8
VSS_5 J2
VSS_6 J8
VSS_7
M1
VSS_8
M9
VSS_9 P1
VSS_10 P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9
G9
K4B4G1646E-BCNB
IC400-*1
SUB_SAMSUNG_DDR
A0
N3
A1
P7
A2 P3
A3 N2
A4
P8
A5
P2
A6 R8
A7 R2
A8
T8
A9
R3
A10/AP L7
A11 R7
A12/BC
N7
A13
T3
NC_5 M7
BA0
M2
BA1 N8
BA2 M3
CK
J7
CK K7
CKE K9
CS
L2
ODT K1
RAS J3
CAS
K3
WE
L3
RESET T2
DQSL F3
DQSL G3
DQSU
C7
DQSU B7
DML
E7
DMU D3
DQL0 E3
DQL1
F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5
H8
DQL6 G2
DQL7 H7
DQU0
D7
DQU1 C3
DQU2 C8
DQU3 C2
DQU4
A7
DQU5 A2
DQU6 B8
DQU7 A3
VREFCA
M8
VREFDQ H1
ZQ L8
VDD_1
B2
VDD_2 D9
VDD_3 G7
VDD_4
K2
VDD_5
K8
VDD_6 N1
VDD_7 N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9
H9
NC_1 J1
NC_2 J9
NC_3
L1
NC_4
L9
A14 T7
VSS_1
A9
VSS_2 B3
VSS_3 E1
VSS_4
G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8
M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12
T9
VSSQ_1 B1
VSSQ_2
B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6
E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9
G9
K4B4G1646E-BCNB
IC402-*1
SUB_SAMSUNG_DDR
A0
N3
A1
P7
A2 P3
A3 N2
A4
P8
A5
P2
A6 R8
A7 R2
A8
T8
A9
R3
A10/AP L7
A11 R7
A12/BC
N7
A13
T3
NC_5 M7
BA0
M2
BA1 N8
BA2 M3
CK
J7
CK K7
CKE K9
CS
L2
ODT K1
RAS J3
CAS
K3
WE
L3
RESET T2
DQSL F3
DQSL G3
DQSU
C7
DQSU B7
DML
E7
DMU D3
DQL0 E3
DQL1
F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5
H8
DQL6 G2
DQL7 H7
DQU0
D7
DQU1 C3
DQU2 C8
DQU3 C2
DQU4
A7
DQU5 A2
DQU6 B8
DQU7 A3
VREFCA
M8
VREFDQ H1
ZQ L8
VDD_1
B2
VDD_2 D9
VDD_3 G7
VDD_4
K2
VDD_5
K8
VDD_6 N1
VDD_7 N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9
H9
NC_1 J1
NC_2 J9
NC_3
L1
NC_4
L9
A14 T7
VSS_1
A9
VSS_2 B3
VSS_3 E1
VSS_4
G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8
M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12
T9
VSSQ_1 B1
VSSQ_2
B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6
E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9
G9
2015-06-13
K2L DDR
K2L
03
1Gbit : T7(NC_6)
DDR3 1.5V bypass Cap - Place these caps near Memory
4Gbit : T7(A14)
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
H5TQ1G63DFR-PBC(x16)
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
Real USE : 1Gbit
later change 60ohm, 1%
later change 60ohm, 1%
Place Near SoC
For ESD
For ESD
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
Copyright © 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only