- 27 -
LGE Internal Use Only
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3. F16 Block Diagram
DDR[0-1
]_DQ[0-1
5]
DDR[0-1
]_A[0:14]/
DDR[0-1
]_BA[2:0]/
DDR3
SD
RA
M
-
1Gbit
(x16
)
-
2133
UART_TX_
0
UART_RX_
1
LO
CK
AN
_Video
A_
F16_CONNECT
F1
6
V
x1
8 la
ne
41
P
V
x1
8 la
ne
51
P
XIN_URSA
XO_URS
A
X-
Ta
l
(24Mhz
)
SPI
FLAS
H
-6
4MB
(x1)
MSPI
_M
IS
O_
M
MSPI
_M
OS
I_
M
I2C_SDA2
I2C_SCL2
LOCKAn_IN
HTPDAn_IN
I2
C_SDA_M1
I2
CS_SCL_M
1
LOCKAn
HTPDAn
T-
CON
POWER
5 Pi
n
PANEL_VC
C
UART_RX_
0
M1
6
Vx1
VI
DEO
8Lan
e
Vx1
OSD 4Lan
e
Data_Format_1
Data_Format_0
DDR3
SD
RA
M
-
1Gbit
(x16)
-
2133
DDR3
SD
RA
M
-
1Gbit
(x16
)
-
2133
I2C_S
Po
rt
4
Pi
n
URSA DEBU
G
Sw
itch
I2
C_SDA7
I2
C_SCL7
I2
CS_SCL
I2
CS_SDA
SDA2_+3.3V_D
B
SCL2_+3.3V_D
B
UART
UART_TX_
1
UART_RX_
1
Jig
Download
UART
UART_TX_
0
UART_RX_
0
UART
for FR
C
UART
for Sy
stem
UART_TX_
1
Data_Format_
0
Data_Format_
1
Summary of Contents for 60UH8500
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