72
Plasma Display Panel Troubleshooting - 2007
ER_IPM
L1
L2
L3
SUS_IPM
P2
ER_LOW
ER_IO
ER_HIGH
Gnd
ER-UP
ER-DN
Gnd
18VDC
Gnd
SUS_DN
SUS_UP
Gnd
18VDC
Chassi GND
SUS_OUT
VS
5VDC
18V IPM
P1
P12
IC1, IC24
P9
5VDC
VA
VA
5VDC
R42
5VDC
VA
Z Bias Circuit
Z Bias Control VR3
Q16,
Q18
D9
D10
D17
P6
To PDP
Output
Waveform TP
To PDP
To PDP
VS
P5
P3
Logic from the Control PCB.
D8
Z
95
V
95V
Vs
Vs
Z
95
V
95V
Vs
Vs
Z
95
V
95V
Vs
Vs
B11
60PC1D Z SUS
Block Diagram
+ C18