LG 55LX9500, Service Manual

Page: 51 / 110

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
/CE
R950
10K
2V5
CONFIG_DONE
R953
1K
OPT
C909
0.1uF
16V
C917
10uF
16V
IC904
EPCS16SI8N_
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
R949
22
R968
22
SYSCLK
R964
22
C920
100pF
50V
X901
54.0000MHz
4
VDD
1
TRISTATE/OPEN
2
GND
3
OUTPUT
C921
10pF
R967
22
2V5
/STATUS
R952
10K
R944 10K
L902
BLM18PG121SN1D
R951
10K
C919
0.1uF
16V
/CONFIG
C903
0.1uF
16V C901
0.1uF
16V
1V2 2V5
C905
0.1uF
16V
2V5
C907
0.1uF
16V
1V2
2V5 1V2
2V5 1V2
LVTX4_A-
LVTX4_C-
SCL2V5
SDA2V5
LVTX4_CLK-
LV
LVTX4_B-
LVTX4_D-
VS_STATUS2V5
MSEL[2]
TA5-
CONFIG_DONE
TB6+
MSEL[0]
2V5
LVTX1_B-
MSEL[1]
TB6-
LVTX1_A-
TCLK5-
LVTX1_D-
TCLK5+
TA5+
1V2
LVTX1_E-
TB5-
LVTX1_C-
SYSCLK
MSEL[3]
TB5+
/RESET2V5
TE6-
TA7-
TB8-
TC8+
TC8-
TD8+
TE8+
TCLK8-
TCLK7-
TCLK8+
TCLK7+
TE6+
TE8-
TD6-
TC6-
TD8-
TA7+
TB7+
TC6+
TCLK6+
2V5
TB7-
TCLK6-
TD6+
TB8+
1V2
MSEL[2]
AR901
22
1/16W
R982 0
OPT
MSEL[0]
MSEL[1]
2V5
R987 0
OPT
R988 0
MSEL[3]
R984 0
OPT
C902
0.1uF
16V
2V5
C904
0.1uF
16V
1V2
C908
0.1uF
16V C906
0.1uF
16V
2V5 1V2
LVTX5_CLK-
LV
LVTX5_B-
LVTX5_C-
LVTX5_A-
TDO
TE2-
/STATUS
TE2+
/CONFIG
ASDO
LVTX8_CLK-
DATA0
LV
DCLK
/CSO
TMS
TDI
TCK
/CE
R993 1K
R991 1K
OPT
2V5
R995
22
R996
22
TCK
TDO
R997
22
TMS
TDI
R994
22
R992 1K
C924
0.1uF
16V
R954 1K
OPT
R948
330
OPT
SW901
JTP-1127WEM
OPT
1 2
4 3
C914
0.1uF
16V
OPT
/3D_FPGA_RESET
R958 4.7K OPT
+3.3V
C911
0.1uF
16V
OPT
IC901
KIA7029AF
OPT
2
G
3
O
1
I
R959
0
OPT
/FPGA_RESET
R963
0
3D_SYNC_OUT
R955
0
R901 100
R903 100
R904 100
R905 100
R937 100
R927 100
R928 100
R930 100
R931 100
R933 100
R938 100
R939 100
R940 100
R941 100
R942 100
LVTX1_CLK-
LV
R1901 100
LV
LVTX2_CLK-
R1902 100
LV
LVTX3_CLK-
R1903 100
LV
LVTX6_CLK-
R1904 100
LV
LVTX7_CLK-
R1905 100
Q901
2SC3052
E
B
C
+3.3V
R1907
10K
R1906
10K
/3D_FPGA_RESET
R1908
10K
Q902
2SC3052
E
B
C
2V5
R1910
22
/RESET2V5
R916 100
LVTX6_E-
LVTX8_B-
R902 100
R935 100
LVTX5_E-
R907 100
R909 100
LVTX6_A-
LVTX5_D-
R906 100
LVTX8_A-
R932 100
R913 100
LVTX8_D-
LVTX7_C-
R934 100
LVTX6_C-
R911 100
LVTX7_B-
R914 100
LVTX8_C-
R910 100
R917 100
LVTX8_E-
R936 100
LVTX7_D-
LVTX6_D-
R915 100
R912 100
LVTX7_A-
LVTX6_B-
R908 100
R926 100
LVTX2_E-
R918 100
LVTX3_D-
LVTX2_D-
R923 100
R921 100
LVTX2_C-
R922 100
LVTX2_B-
R943 100
LVTX2_A-
R919 100
LVTX3_C-
R929 100
LVTX4_E-
LVTX3_A-
R925 100
LVTX3_B-
R920 100
R924 100
LVTX3_E-
LVTX7_E-
TD2+
TD2-
TD1-
TD1+
TA1-
TA1+
TE3+
TE3-
TE4+
TE4-
TC2+
TC2-
TA2+
TA2-
TE1+
TE1-
TB1+
TB1-
TD3+
TD3-
TD4+
TD4-
TB2-
TB2+
TC1+
TC1-
TCLK2-
TCLK2+
TCLK1+
TCLK1-
TB4+
TB4-
TC4+
TC4-
TC3+
TC3-
TA3-
TA3+
TA4+
TA4-
TB3-
TB3+
TCLK3+
TCLK3-
TCLK4+
TCLK4-
TA6-
TA6+
TE5-
TE5+
TC5-
TC5+
TD5+
TD5-
TE7+
TE7-
TA8+
TA8-
TD7+
TD7-
TC7+
TC7-
2V5 +3.3V
VS_STATUS2V5
R1925
22
OPT R1921
22 OPT
R1922 5.6K R1923 2K R1924 4.7K
OPT
Q905
FDV301N
G
D S
R1914 5.6K OPT
Q903
FDV301N
G
D S
2V5 +3.3V
R1911
22
R1913 2K
I2C_SDA
R1918 2K
R1916
22
2V5 +3.3V
Q904
FDV301N
G
D S
R1919 5.6K OPT
I2C_SCL
R1909
4.7K
+3.3V
R1928
22
Q907
2SC3052
E
B
C
R1932
10K
R1931
10K
R1930
10K
Q906
2SC3052
E
B
C
+3.3V
VS_STATUS2V5
FPGA_SDA
FPGA_SCL
SDA2V5
SCL2V5
C910
18pF
50V
OPT
C913
18pF
50V
OPT
R1915
0
R1920
0
R1926
0
OPT
R1927
0
OPT
C915
18pF
50V
OPT
R1929
3.3K
IC1000
EP3C55F484C6N
A11
B8_IO[0]
B11
B8_IO[1]
D10
B8_IO[2]
E10
B8_IO[3]
A10
B8_IO[4]
B10
B8_IO[5]
A9
B8_IO[6]
B9
B8_IO[7]
C10
B8_IO[8]
G11
B8_IO[9]
A8 B8_IO[10]
B8
B8_IO[11]
A7
B8_IO[12]
B7
B8_IO[13]
A6
B8_IO[14]
B6
B8_IO[15]
E9
B8_IO[16]
C8
B8_IO[17]
C7
B8_IO[18]
D8
B8_IO[19]
E8
B8_IO[20]
A5
B8_IO[21]
B5
B8_IO[22]
G10
B8_IO[23]
F10
B8_IO[24]
C6
B8_IO[25]
D7
B8_IO[26]
A4
B8_IO[27]
B4
B8_IO[28]
F8
B8_IO[29]
G8
B8_IO[30]
A3
B8_IO[31]
B3
B8_IO[32]
D6 B8_IO[33]
E7
B8_IO[34]
C3
B8_IO[35]
C4
B8_IO[36]
F7
B8_IO[38]
G7
B8_IO[39]
F9
B8_IO[40]
E6
B8_IO[41]
E5
B8_IO[42]
G9
B8_IO[43]
IC1000
EP3C55F484C6N
F6
VCCD_PLL3
F5
GNDA3
G6
VCCA3
G4
B1_IO[0]
G3
B1_IO[1]
B2
B1_IO[2]
B1
B1_IO[3]
G5
B1_IO[4]
E4
B1_IO[5]
E3 B1_IO[6]
C2
B1_IO[7]
C1
B1_IO[8]
D2
B1_IO[9]
D1
B1_IO[10]
H7
B1_IO[11]
H6
B1_IO[12]
J6
B1_IO[13]
H4
B1_IO[14]
H3
B1_IO[15]
E2
B1_IO[16]
E1
B1_IO[17]
F2
B1_IO[18]
F1
B1_IO[19]
J5
B1_IO[20]
H5
B1_IO[21]
K6
nSTATUS
J7
B1_IO[22]
K7
B1_IO[23]
J4
B1_IO[24]
H2
B1_IO[25]
H1
B1_IO[26]
J3
B1_IO[27]
J2 B1_IO[28]
J1
B1_IO[29]
K2
DCLK
K1
B1_IO[30]
K5
nCONFIG
L5
TDI
L2
TCK
L1
TMS
L4
TDO
L3
nCE
G2
CLK0
G1
CLK1
IC1000
EP3C55F484C6N
T2
CLK2
T1
CLK3
L6
B2_IO[0]
M6
B2_IO[1]
M2
B2_IO[2]
M1
B2_IO[3]
M4
B2_IO[4]
M3
B2_IO[5]
N2
B2_IO[6]
N1
B2_IO[7]
M5 B2_IO[8]
P2
B2_IO[9]
P1
B2_IO[10]
R2
B2_IO[11]
R1
B2_IO[12]
N5
B2_IO[13]
P4
B2_IO[14]
P3
B2_IO[15]
U2
B2_IO[16]
U1
B2_IO[17]
V2
B2_IO[18]
V1
B2_IO[19]
P5
B2_IO[20]
N6
B2_IO[21]
R4
B2_IO[22]
R3
B2_IO[23]
W2
B2_IO[24]
W1
B2_IO[25]
Y2
B2_IO[26]
Y1
B2_IO[27]
T3
B2_IO[28]
N7
B2_IO[29]
P7
B2_IO[30]
AA2 B2_IO[31]
AA1
B2_IO[32]
V4
B2_IO[33]
V3
B2_IO[34]
P6
B2_IO[35]
R5
B2_IO[36]
T4
B2_IO[37]
T5
B2_IO[38]
R6
B2_IO[39]
T6
VCCA1
U5
GNDA1
U6
VCCD_PLL1
IC1000
EP3C55F484C6N
F16
B7_IO[0]
E16
B7_IO[1]
F15
B7_IO[2]
G16
B7_IO[3]
G15
B7_IO[4]
F14
B7_IO[5]
C18
B7_IO[6]
D18
B7_IO[7]
D17
B7_IO[8]
C19
B7_IO[9]
D19
B7_IO[10]
A20
B7_IO[11]
B20 B7_IO[12]
C17
B7_IO[13]
B19 B7_IO[14]
A19
B7_IO[15]
A18
B7_IO[16]
B18
B7_IO[17]
D15
B7_IO[18]
E15
B7_IO[19]
G14
B7_IO[20]
G13
B7_IO[21]
A17
B7_IO[22]
B17
B7_IO[23]
A16
B7_IO[24]
B16
B7_IO[25]
C15
B7_IO[26]
E14
B7_IO[27]
F13
B7_IO[28]
A15
B7_IO[29]
B15
B7_IO[30]
C13
B7_IO[31]
D13
B7_IO[32]
E13
B7_IO[33]
A14
B7_IO[34]
B14 B7_IO[35]
A13
B7_IO[36]
B13
B7_IO[37]
E12
B7_IO[38]
E11
B7_IO[39]
F11
B7_IO[40]
A12
CLK8
B12
CLK9
IC1000
EP3C55F484C6N
G22
CLK5
G21
CLK4
M18
CONF_DONE
M17
MSEL0
L18
MSEL1
L17
MSEL2
K20
MSEL3
L22
B6_IO[0]
L21
B6_IO[1]
K19
B6_IO[2]
K22
B6_IO[3]
K21
B6_IO[4]
J22 B6_IO[5]
J21
B6_IO[6]
H22 B6_IO[7]
H21
B6_IO[8]
K17
B6_IO[9]
K18
B6_IO[10]
J18
B6_IO[11]
F22
B6_IO[12]
F21
B6_IO[13]
J20
B6_IO[14]
J19
B6_IO[15]
J17
B6_IO[16]
H20
B6_IO[17]
H19
B6_IO[18]
E22
B6_IO[19]
E21
B6_IO[20]
H18
B6_IO[21]
H16
B6_IO[22]
D22
B6_IO[23]
D21
B6_IO[24]
F20
B6_IO[25]
F19
B6_IO[26]
G18
B6_IO[27]
H17 B6_IO[28]
C22
B6_IO[29]
C21
B6_IO[30]
B22
B6_IO[31]
B21
B6_IO[32]
C20
B6_IO[33]
D20
B6_IO[34]
F17
B6_IO[35]
G17
B6_IO[36]
F18
VCCA2
E18
GNDA2
E17
VCCD_PLL2
IC1000
EP3C55F484C6N
V17
VCCD_PLL4
V18
GNDA4
U18
VCCA4
AA22
B5_IO[0]
AA21
B5_IO[1]
T17
B5_IO[2]
T18
B5_IO[3]
W20
B5_IO[4]
W19
B5_IO[5]
Y22
B5_IO[6]
Y21
B5_IO[7]
U20
B5_IO[8]
U19 B5_IO[9]
W22
B5_IO[10]
W21 B5_IO[11]
T20
B5_IO[12]
T19
B5_IO[13]
R17
B5_IO[14]
P17
B5_IO[15]
V22
B5_IO[16]
V21
B5_IO[17]
R20
B5_IO[18]
U22
B5_IO[19]
U21
B5_IO[20]
R18
B5_IO[21]
R19
B5_IO[22]
N16
B5_IO[23]
R22
B5_IO[24]
R21
B5_IO[25]
P20
B5_IO[26]
P22
B5_IO[27]
P21
B5_IO[28]
N20
B5_IO[29]
N19
B5_IO[30]
N17
B5_IO[31]
N18 B5_IO[32]
N22
B5_IO[33]
N21
B5_IO[34]
M22
B5_IO[35]
M21
B5_IO[36]
M20
B5_IO[37]
M19
B5_IO[38]
M16
B5_IO[39]
T22
CLK7
T21
CLK6
R965
27
R1912 2K
R1917 2K
TDI_FLASH
/CSO
R946
0
EJTAG_TO_FLASH
R945
0
EJTAG_TO_FLASH
TMS_FLASH
DATA0
R956
0
EJTAG_TO_FLASH
TDO_FLASH
DCLK
ASDO
R947
0
EJTAG_TO_FLASH
TCK_FLASH
P901
12505WR-10
1
2
3
4
5
6
7
8
9
10
11
MDS62110201
GAS1-*1
GAS1_4.5T(8x5)
MDS62110201
GAS2-*1
GAS2_4.5T(8x5)
MDS62110201
GAS3-*1
GAS3_4.5T(8x5)
MDS62110201
GAS4-*1
GAS4_4.5T(8x5)
MDS62110201
GAS7-*1
GAS7_4.5T(8x5)
MDS62110201
GAS5-*1
GAS5_4.5T(8x5)
MDS62110201
GAS8-*1
GAS8_4.5T(8x5)
MDS62110201
GAS6-*1
GAS6_4.5T(8x5)
MDS62110201
GAS11-*1
GAS11_4.5T(8x5)
MDS62110201
GAS9-*1
GAS9_4.5T(8x5)
MDS62110201
GAS12-*1
GAS12_4.5T(8x5)
MDS62110201
GAS10-*1
GAS10_4.5T(8x5)
R2237
4.7K
R2236
10K
R2239
0
/CONFIG
FPGA_D/L_CTRL
Q908
2SC3052
E
B
C
2V5
/CE
R2238
22
MDS62110208
GAS9
GAS9_4.5T(8x6)
MDS62110208
GAS1
GAS1_4.5T(8x6)
MDS62110208
GAS8
GAS8_4.5T(8x6)
MDS62110208
GAS7
GAS7_4.5T(8x6)
MDS62110208
GAS3
GAS3_4.5T(8x6)
MDS62110208
GAS11
GAS11_4.5T(8x6)
MDS62110208
GAS5
GAS5_4.5T(8x6)
MDS62110208
GAS10
GAS10_4.5T(8x6)
MDS62110208
GAS12
GAS12_4.5T(8x6)
MDS62110208
GAS4
GAS4_4.5T(8x6)
MDS62110208
GAS2
GAS2_4.5T(8x6)
MDS62110208
GAS6
GAS6_4.5T(8x6)
MDS62110204
GAS7-*2
GAS7_5.5T(8x6)
MDS62110204
GAS4-*2
GAS4_5.5T(8x6)
MDS62110204
GAS8-*2
GAS8_5.5T(8x6)
MDS62110204
GAS5-*2
GAS5_5.5T(8x6)
MDS62110204
GAS2-*2
GAS2_5.5T(8x6)
MDS62110204
GAS1-*2
GAS1_5.5T(8x6)
MDS62110204
GAS11-*2
GAS11_5.5T(8x6)
MDS62110204
GAS6-*2
GAS6_5.5T(8x6)
MDS62110204
GAS9-*2
GAS9_5.5T(8x6)
MDS62110204
GAS12-*2
GAS12_5.5T(8x6)
MDS62110204
GAS10-*2
GAS10_5.5T(8x6)
MDS62110204
GAS3-*2
GAS3_5.5T(8x6)
2V5
+3.3V
L901
BLM18PG121SN1D
OPT
R986 0
R983 0 R989 0
OPT
R985 0
EP3C55_C6N (FPGA IC) 10 9
3D + 240 FRC + TCON BOARD 2009. 11. 13
IR Emitter Vsync Level Shift (2.5V to 3.3V)
FPGA Reset Level Shifter (3.3V to 2.5V)
FPGA I2C Level Shift (3.3V <-> 2.5V)
FPGA DOWNLOAD CONTROL
SMD Gasket - 4.5T (8x6)
SMD Gasket - 4.5T (8x5)
SMD Gasket - 5.5T (8x6)
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only