THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C-MDQU7
I2C_SDA
C-MDQU0
C-TMA12
FRC_MODEL_OPT_0
C-MA1
C-TMA0
RXA0-
C-MDQU7
C-TMDQL5
RXB0-
1K
R
33
8
O
PT
VCC1.5V_U3_DDR
C-TMA6
C-MBA2
C-MA11
0
.1
u
F
C
31
7
L/DIM_SCLK
RXC0+
C-MDQU2
RXCCK+
RXACK-
RXA1+
C-TMA3
C-MDML
FRC_PWM1
C-MBA0
C-TMA0
22
R334
OPT
C-MDQL2
C-MA7
22
R307
RXA1-
RXD2+
C-TMCKB
C-TMDQU1
0
.1
u
F
C
30
6
C-TMCKE
10
OPT
R330
C-TMA7
C-TMA12
10
R329
OPT
C-MDQSU
RXD1+
1K
R
32
3
55
IN
C
H
C-MA4
1
0
0
0
p
F
C
30
4
C-TMRESETB
22
R311
FRC_CONF0
+1.5V_FRC_DDR
1K
1%
R
30
1
C-TMA4
C-MDQU5
RXD4+
0
.1
u
F
C
32
0
1K
R
32
5
55
IN
C
H
RXA2-
FRC_SPI_SDI
1
0
u
F
C
30
1
C-MDQU6
C-TMDQU5
RXCCK-
FRC_MODEL_OPT_2
1K
O
PT
R
32
2
C-TMA5
+3.3V_Normal
C-TMDQU4
C-TMDQL0
C-TMDQU5
2D/3D_CTL
C-TMA11
C-MA5
VCC1.5V_U3_DDR
C-MODT
C-TMDMU
RXA2+
C-TMA10
22
AR308
22
AR309
C-MBA0
C-MDQSLB
C-MDQU2
RXB4-
FRC_SPI_SCK
C-MA2
C-MVREFDQ
C-TMDML
C-TMDQL6
C-MCK
C-MCKE
C-MDQL6
C-MCKB
C-TMCKB
1K
R
34
1
O
PT
22
R316
RXB1-
C-TMA6
22
AR303
820
R317
55INCH
C-TMDQU6
C-MA9
RXB1+
1K
O
PT
R
32
1
C-MA3
0
.1
u
F
C
30
5
C-TMDQL4
FRC_SPI_SDI
C-TMDQU6
C-MDQL4
0
.1
u
F
C
32
3
C-MA7
C-MDQL3
FRC_PWM1
33
R300
OPT
22
AR307
C-MDQSL
22
AR305
C-TMA9
C-TMDQU4
C-MDQSL
22
R314
RXA3+
0
.1
u
F
C
30
8
10
OPT
R327
RXC4+
0
.1
u
F
C
32
2
22
R313
FRC_/SPI_CS
C-MRASB
C-TMDQL7
C-TMCKE
RXB4+
C-MDQL3
2D/3D_CTL
RXD3+
C-MA1
FRC_PWM0
RXDCK-
C-TMA3
RXD0+
C-TMRASB
RXC2-
C-TMDQU7
VCC1.5V_U3_DDR
C-TMDQU3
C-MDML
0
.1
u
F
C
31
6
RXB0+
0
.1
u
F
C
30
3
OPT
C-TMA8
C-TMA2
C-TMDQSL
0
.1
u
F
C
31
8
RXA3-
0
.1
u
F
C
31
0
C-TMDQL2
C-MA12
C-TMCK
22
R308
C-TMDQL1
C-TMA7
1K
O
PT
R
34
0
FRC_MODEL_OPT_0
C-MDQU3
RXD4-
1
0
0
0
p
F
C
31
4
C-MA10
1K
O
PT
R
34
3
FRC_CONF0
C-MDQU5
C-MVREFCA
C-TMBA0
22
R309
RXBCK-
C-TMDQL4
C-MBA1
RXA4+
C-MDQU6
0
.1
u
F
C
31
9
C-MWEB
C-TMCASB
0
.1
u
F
C
30
2
RXB2+
C-MDQU1
C-MA10
C-MBA2
C-MVREFCA
22
R310
C-MDQSLB
0
.1
u
F
C
32
1
C-TMDQL3
C-TMDQU0
VCC1.5V_U3_DDR
RXD1-
FRC_SDA
C-TMA10
C-MA4
22
R312
FRC_MODEL_OPT_1
C-MDQU4
RXC4-
C-TMBA2
FRC_CONF1
1
5
0
O
PT
R
30
6
C-MDMU
C-TMDQSUB
240
1%
R303
1K
O
PT
R
31
9
22
R335
OPT
C-TMODT
1K
1%
R
30
5
C-TMDQSU
C-TMBA1
C-TMA9
C-MDQSU
C-TMDQSU
10
OPT
R328
C-MDQU0
C-MCK
C-MCASB
C-TMBA1
C-MA12
C-MDQU4
C-MDQSUB
C-TMDQU1
C-MA9
0
.1
u
F
C
31
3
C-TMDQU3
C-TMBA0
FRC_SPI_SDO
C-TMA1
0
.1
u
F
C
31
2
1K
O
PT
R
33
6
C-MRESETB
1K
R
31
8
55
IN
C
H
RXC3-
C-TMDQSL
I2C_SCL
L301
C-TMDQL3
RXC1+
C-TMBA2
FRC_PWM0
RXA4-
C-MA6
C-MDQL7
FRC_/SPI_CS
22
R326
55INCH
C-MA8
C-TMWEB
C-MDQL2
C-TMDQL2
C-TMDQU2
C-TMDQL7
C-TMA8
0
.1
u
F
C
31
1
0
.1
u
F
C
31
5
C-MCKB
C-MA11
C-MWEB
C-MA0
V_SYNC
22
AR301
1K
O
PT
R
32
4
C-TMDML
C-MDQL0
0.1uF
16V
C325
FRC_SPI_SCK
C-MA5
C-MDQL1
C-MDQL1
C-MDQL6
C-TMCK
RXC1-
10
K
R
34
9
O
PT
RXC3+
RXACK+
C-MODT
RXB3+
RXD2-
1K
R
33
9
C-MDQSUB
RXBCK+
C-TMDQSLB
22
R331
55INCH
33
OPT
R348
1K
1%
R
30
4
1K
O
PT
R
34
2
1K
O
PT
R
33
7
C-TMDQL1
C-TMA1
RXD3-
RXDCK+
C-TMRESETB
RXC2+
C-TMWEB
C-MRASB
C-MA3
L/DIM_MOSI
22
AR304
C-MA6
33
R332
OPT
RXD0-
C-TMA5
RXB3-
22
AR302
0
.1
u
F
C
30
7
+3.3V_Normal
C-TMA11
FRC_SPI_SDO
1K
R
32
0
55
IN
C
H
C-TMDQL0
0
.1
u
F
C
30
9
10K
R333
C-TMDMU
C-TMCASB
C-MA8
C-TMA2
C-TMDQU7
C-MA2
10uF
10V
C324
C-TMA4
C-MCKE
C-MBA1
+3.3V_Normal
FRC_MODEL_OPT_2
C-MDQL0
C-TMDQL5
C-MDMU
VCC1.5V_U3_DDR
4
.7
K
R
35
0
O
PT
C-MVREFDQ
FRC_SCL
C-TMDQSUB
1K
1%
R
30
2
+3.3V_Normal
22
AR306
C-MDQU3
C-MA0
22
R315
FRC_MODEL_OPT_1
C-MDQL5
RXA0+
C-TMDQSLB
C-MDQL7
C-TMDQL6
C-MDQL4
RXB2-
C-TMRASB
C-MRESETB
C-TMDQU0
C-MDQU1
FRC_CONF1
C-MDQL5
VCC1.5V_U3_DDR
C-TMODT
RXC0-
C-TMDQU2
C-MCASB
LGE107DC-RP [S7M+ DIVX/MS10]
IC101
S7M-PLUS_DivX_MS10
FRC_DDR3_A0/DDR2_NC
AE1
FRC_DDR3_A1/DDR2_A6
AF16
FRC_DDR3_A2/DDR2_A7
AF1
FRC_DDR3_A3/DDR2_A1
AE3
FRC_DDR3_A4/DDR2_CASZ
AD14
FRC_DDR3_A5/DDR2_A10
AD3
FRC_DDR3_A6/DDR2_A0
AF15
FRC_DDR3_A7/DDR2_A5
AF2
FRC_DDR3_A8/DDR2_A2
AE15
FRC_DDR3_A9/DDR2_A9
AD2
FRC_DDR3_A10/DDR2_A11
AD16
FRC_DDR3_A11/DDR2_A4
AD15
FRC_DDR3_A12/DDR2_A8
AE16
FRC_DDR3_BA0/DDR2_BA2
AF3
FRC_DDR3_BA1/DDR2_ODT
AF14
FRC_DDR3_BA2/DDR2_A12
AD1
FRC_DDR3_MCLK/DDR2_MCLK
AD13
FRC_DDR3_CKE/DDR2_RASZ
AE14
FRC_DDR3_MCLKZ/DDR2_MCLKZ
AE13
FRC_DDR3_ODT/DDR2_BA1
AE4
FRC_DDR3_RASZ/DDR2_WEZ
AD5
FRC_DDR3_CASZ/DDR2_CKE
AF4
FRC_DDR3_WEZ/DDR2_BA0
AD4
FRC_DDR3_RESETB/DDR2_A3
AE2
FRC_DDR3_DQSL/DDR2_DQS0
AF8
FRC_DDR3_DQSLB/DDR2_DQSB0
AD9
FRC_DDR3_DQSU/DDR2_DQS1
AE9
FRC_DDR3_DQSUB/DDR2_DQSB1
AF9
FRC_DDR3_DML/DDR2_DQ7
AE11
FRC_DDR3_DMU/DDR2_DQ11
AF6
FRC_DDR3_DQL0/DDR2_DQ6
AE6
FRC_DDR3_DQL1/DDR2_DQ0
AF11
FRC_DDR3_DQL2/DDR2_DQ1
AD6
FRC_DDR3_DQL3/DDR2_DQ2
AD12
FRC_DDR3_DQL4/DDR2_DQ4
AE5
FRC_DDR3_DQL5/DDR2_NC
AF12
FRC_DDR3_DQL6/DDR2_DQ3
AF5
FRC_DDR3_DQL7/DDR2_DQ5
AE12
FRC_DDR3_DQU0/DDR2_DQ8
AE10
FRC_DDR3_DQU1/DDR2_DQ14
AF7
FRC_DDR3_DQU2/DDR2_DQ13
AD11
FRC_DDR3_DQU3/DDR2_DQ12
AD7
FRC_DDR3_DQU4/DDR2_DQ15
AD10
FRC_DDR3_DQU5/DDR2_DQ9
AE7
FRC_DDR3_DQU6/DDR2_DQ10
AF10
FRC_DDR3_DQU7/DDR2_DQM1
AD8
FRC_DDR3_NC/DDR2_DQM0
AE8
FRC_VSYNC_LIKE
Y11
FRC_TESTPIN
Y19
ACKP/RLV3P/RED[3]
W26
ACKM/RLV3N/RED[2]
W25
A0P/RLV0P/RED[9]
U26
A0M/RLV0N/RED[8]
U25
A1P/RLV1P/RED[7]
U24
A1M/RLV1N/RED[6]
V26
A2P/RLV2P/RED[5]
V25
A2M/RLV2N/RED[4]
V24
A3P/RLV4P/RED[1]
W24
A3M/RLV4N/RED[0]
Y26
A4P/RLV5P/GREEN[9]
Y25
A4M/RLV5N/GREEN[8]
Y24
BCKP/TCON13/GREEN[1]
AC26
BCKM/TCON12/GREEN[0]
AC25
B0P/RLV6P/GREEN[7]
AA26
B0M/RLV6N/GREEN[6]
AA25
B1P/RLV7P/GREEN[5]
AA24
B1M/RLV7N/GREEN[4]
AB26
B2P/RLV8P/GREEN[3]
AB25
B2M/RLV8N/GREEN[2]
AB24
B3P/TCON11/BLUE[9]
AC24
B3M/TCON10/BLUE[8]
AD26
B4P/TCON9/BLUE[7]
AD25
B4M/TCON8/BLUE[6]
AD24
CCKP/LLV3P
AD23
CCKM/LLV3N
AE23
C0P/LLV0P/BLUE[5]
AE26
C0M/LLV0N/BLUE[4]
AE25
C1P/LLV1P/BLUE[3]
AF26
C1M/LLV1N/BLUE[2]
AF25
C2P/LLV2P/BLUE[1]
AE24
C2M/LLV2N/BLUE[0]
AF24
C3P/LLV4P
AF23
C3M/LLV4N
AD22
C4P/LLV5P
AE22
C4M/LLV5N
AF22
DCKP/TCON5
AD19
DCKM/TCON4
AE19
D0P/LLV6P
AD21
D0M/LLV6N
AE21
D1P/LLV7P
AF21
D1M/LLV7N
AD20
D2P/LLV8P
AE20
D2M/LLV8N
AF20
D3P/TCON3
AF19
D3M/TCON2
AD18
D4P/TCON1
AE18
D4M/TCON0
AF18
GPIO0/TCON15/HSYNC/VDD_ODD
AB22
GPIO1/TCON14/VSYNC/VDD_EVEN
AB23
GPIO2/TCON7/LDE/GCLK4
AC23
GPIO3/TCON6/LCK/GCLK2
AC22
FRC_SPI_CZ
AB16
FRC_GPIO1
AA14
FRC_SPI1_CK
AC15
FRC_GPIO8
Y16
FRC_SPI_DO
AC16
FRC_SPI1_DI
AC14
FRC_SPI_CK
AA16
FRC_SPI_DI
AA15
FRC_I2CS_DA
Y10
FRC_I2CS_CK
AA11
FRC_PWM0
AB15
FRC_PWM1
AB14
H5TQ1G63DFR-H9C
EAN61828901
IC301
XI
N
Y
H
_
3
3
3
1
_
R
D
D
_
C
R
F
_
H
C
NI
5
5
_a
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ1G63DFR-PBC
EAN61829001
IC301-*2
FRC_DDR_1600_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
W25X20BVSNIG
IC302
OPT
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
K4B1G1646G-BCH9
EAN61857101
IC301-*3
FRC_DDR_1333_SS_NEW
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
NT5CB64M16DP-CF
EAN61857201
IC301-*4
FRC_DDR_1333_NANYA_NEW
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12
N7
NC_6
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_7
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
$ 0 . 1 7
CLose to Saturn7M IC
(FRC_CONF0)
Close to DDR Power Pin
<U3 CHIP Config>
CLose to DDR3
(FRC_CONF1,FRC_PWM1, FRC_PWM0)
DDR3 1.5V By CAP - Place these Caps near Memory
3 ’ d 5 : b o o t f r o m i n t e r n a l S R A M
3’d6 : boot from EEPROM
3 ’ d 7 : b o o t f o r m S P I f l a s h
HIGH : I2C ADR = B8
LOW : I2C ADR = B4
GP2R
FRC_DDR
20101023
3
Copyright
©
2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 55LV355C-UA
Page 47: ......
