
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
0 . 0 4 7 u F
C222
2 . 2 u F
C237
PC_LIN
AUDIO_MASTER_CLK
KDS181
D200
OPT
0 . 0 4 7 u F
C233
2 . 2 u F
C243
4 . 7 u F
C248
USB1_DP_to_MAIN
0 . 1 u F
C251
0 . 0 4 7 u F
C226
MODEL_OPT_4
2 . 2 u F
C240
1M
R244
COMP1_RIN
MS_LRCK
2 . 2 u F
C242
0 . 0 4 7 u F
C230
2 . 2 u F
C241
0 . 0 4 7 u F
C229
MS_LRCH
22
R239
COMP1_LIN
+3.3V
2 . 2 u F
C247
SOC_RESET
2 . 2 u F
C244
DSUB_R-
SOC_RESET
DSUB_VSYNC
0 . 0 4 7 u F
C203
0 . 0 4 7 u F
C224
1000pF
C204
62K
R200
OPT
4.7K
R256
OPT
DSUB_R
0 . 0 4 7 u F
C218
DSUB_B
24MHz
X200
SCL1
0 . 0 4 7 u F
C215
0 . 0 4 7 u F
C216
0 . 1 u F
C253
0 . 0 4 7 u F
C227
0 . 0 4 7 u F
C228
DSUB_G
2 . 2 u F
C246
C
DSUB_G-
0 . 0 4 7 u F
C231
4 . 7 u F
10V
C200
OPT
22
R236
22
R237
+3.3V
MODEL_OPT_5
0 . 0 4 7 u F
C219
2K
R235
DSUB_HSYNC
47
R255
2K
R234
0 . 0 4 7 u F
C213
PC_RIN
68
R214
0 . 1 u F
C234
OPT
0 . 0 4 7 u F
C220
0 . 1 u F
C235
OPT
0 . 0 4 7 u F
C217
22
R238
MS_SCK
1000pF
C205
0 . 0 4 7 u F
C214
C
DSUB_B-
2 . 2 u F
C236
2 . 2 u F
C245
0
R223
4.7K
R257
OPT
SDA1
USB1_DM_to_MAIN
10uF
C250
22
R206
10K
R203
10K
R201
22
R205
68
R216
68
R212
68
R209
0
R217
10
R202
OPT
22
R210
OPT
10K
R231
DVI_DDC_SDA
DVI_DDC_SCL
0 . 1 u F
16V
C202
OPT
IR
SUB_SDA_NEC_TEMP
SUB_SCL_NEC_TEMP
1uF
C249
33
R225
33
R224
33
R220
33
R219
33
R222
33
R227
33
R207
33
R226
33
R221
33
R228
33
R208
33
R218
HDMI_CEC_S7
0
R204
24pF
C257
24pF
C258
22
R229
22
R230
22
R233
22
R232
10K
R254
OPT
0 . 0 4 7 u F
C261
0 . 0 4 7 u F
C262
0 . 0 4 7 u F
C263
TMDS_DEMUX_SCL
TMDS_DEMUX_SDA
0
OPT
R241
0
R247
DDC_SDA
DDC_SCL
C-TMDQL3
C-TMDQL6
C-TMCKE
C-TMBA2
C-TMA3
C-TMDQU7
C-TMA12
C-TMDQU5
C-TMDQSLB
C-TMDQSUB
C-TMA0
C-TMODT
C-TMDQL7
C-TMA11
C-TMDQL0
C-TMBA0
C-TMDQU1
C-TMDQL2
C-TMDQU0
C-TMA2
C-TMDQU4
C-TMDMU
C-TMDML
C-TMDQSU
C-TMA1
C-TMCK
C-TMWEB
C-TMRESETB
C-TMDQU6
C-TMA8
C-TMRASB
C-TMDQU2
C-TMBA1
C-TMA4
C-TMA6
C-TMA7
C-TMCKB
C-TMA9
C-TMCASB
C-TMDQL5
C-TMA5
C-TMDQU3
C-TMDQSL
C-TMA10
C-TMDQL1
C-TMDQL4
C-TMDQU4
C-TMDQU3
C-TMA10
C-TMDQL4
10
OPT
R281
C-TMA3
C-MDQSL
10
OPT
R286
C-MDQSU
10
OPT
AR206
10
OPT
AR201
C-MCKE
C-MA9
C-TMBA0
C-TMA7
C-TMA1
C-MDQU1
C-MDQU6
C-TMDQL6
C-MDQL6
C-TMA6
C-MRASB
C-TMCKB
10
OPT
R284
C-TMCASB
10
OPT
AR208
C-MA0
C-TMA12
10
OPT
AR209
C-MA8
C-MCKB
C-TMDML
C-MDQU4
C-TMDQU1
C-MDQU7
C-TMDQU7
C-MDML
C-TMA5
C-TMDQU5
C-MA10
C-TMBA1
C-TMCKE
C-TMDQL1
C-MA6
C-MDQU2
C-MBA0
10
OPT
R279
C-TMDQL3
C-MA1
C-MRESETB
C-TMA0
10
OPT
AR205
C-TMDQU0
C-MA3
C-TMCK
C-MDQL3
10
OPT
AR204
10
OPT
R283
10
OPT
AR203
C-TMRESETB
C-MDQL0
C-TMA8
C-MBA1
10
OPT
R288
10
OPT
R282
C-MDQL4
C-TMDQL0
C-TMDMU
C-MCASB
C-MDQSUB
C-TMDQU6
10
OPT
R287
10
OPT
R285
C-MDQU0
C-MA5
C-TMRASB
C-TMDQL2
C-TMBA2
10
OPT
R280
C-MDQSLB
C-MA11
C-TMDQU2
C-MDQL1
C-MDQL5
C-TMDQSU
C-TMA4
C-MA4
C-TMODT
C-MDMU
C-MA2
C-TMWEB
C-MWEB
10
OPT
AR207
C-MA12
C-MDQL7
C-TMDQL5
C-TMDQSL
C-MDQL2
C-MODT
10
OPT
AR202
C-TMA11
C-MDQU5
C-TMA9
C-TMDQSUB
C-MDQU3
C-TMA2
C-MCK
C-TMDQSLB
C-MBA2
C-TMDQL7
C-MA7
C-MA9
C-MDMU
C-MDQU3
C-MDQL4
C-MDQSL
C-MBA0
C-MA0
C-MDQU6
10K
OPT
R278
H5TQ1G63BFR-12C
FRC_DDR_1600
IC201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C-MCASB
C-MA4
C-MDQL1
C-MDQU0
C-MDQU5
C-MA2
C-MDQL3
C-MDQU2
C-MA10
C-MVREFDQ
C-MA7
C-MDQU7
C-MA12
C-MDQU4
C-MODT
C-MBA1
C-MA3
C-MA1
C-MRASB
150
OPT
R277
C-MA11
C-MA6
C-MDQL2
C-MCKB
C-MA8
C-MDQSUB
C-MBA2
C-MRESETB
C-MDQL7
C-MDQL0
VCC1.5V_U3_DDR
C-MVREFCA
C-MCKE
C-MDQSU
C-MWEB
C-MDQSLB
240
1%
OPT
R276
C-MDQU1
C-MDQL5
C-MCK
VCC1.5V_U3_DDR
C-MA5
C-MDML
C-MDQL6
RXB3+
RXBCK+
RXB2+
RXB0-
RXB4+
RXB0+
RXB3-
RXB4-
RXB1-
RXB1+
RXBCK-
RXB2-
RXC3-
RXC0+
RXD2-
RXCCK-
RXD1-
RXD2+
RXC4-
RXD0-
RXC4+
RXC1+
RXD4+
RXDCK+
RXDCK-
RXD4-
RXD0+
RXD1+
RXCCK+
RXC2-
RXC1-
RXD3-
RXC2+
RXC3+
RXC0-
RXD3+
TP200
FRC_PWM1
FRC_PWM0
FRC_CONF1
0
OPT
R242
22
OPT
R290
I2C_SDA
22
OPT
R291
I2C_SCL
FRC_CONF0
TP201
RXACK-
RXA3-
RXA2+
RXACK+
RXA1-
RXA2-
RXA0-
RXA4+
RXA1+
RXA3+
RXA0+
RXA4-
1K
100/120Hz LVDS
R263
1K
NO_FRC
R272
1K
LCD
R260
1K
MINI_LVDS
R269
100
3D
R258
100
R248
100
R249
1K
50/60Hz LVDS
R264
1K
HD
R266
1K
OLED
R259
1K
LVDS
R270
MODEL_OPT_4
MODEL_OPT_6
MODEL_OPT_3
MODEL_OPT_0
1K
FHD
R265
1K
GIP
R261
+3.3V
1K
FRC
R271
MODEL_OPT_1
100
3D
R252
MODEL_OPT_5
1K
DDR_256MB
R268
1K
DDR_512MB
R267
100
R250
1K
NON_GIP
R262
MODEL_OPT_2
100
R240
+3.3V
22
OPT
R274
FRC_RESET
10K
OPT
R275
10K
OPT
R273
1K
OPT
R296
1K
OPT
R251
+3.3V
FRC_PWM0
FRC_PWM1
FRC_CONF1
FRC_CONF0
1K
OPT
R298
1K
OPT
R253
1K
OPT
R299
1K
OPT
R243
1K
OPT
R289
1K
OPT
R297
0.1uF
OPT
C232
1K
1%
OPT
R295
1000pF
OPT
C206
1K
1%
OPT
R294
OPT
L202
VCC1.5V_U3_DDR
0.1uF
OPT
C256
0.1uF
OPT
C210
10uF
OPT
C209
VCC1.5V_U3_DDR
1K
1%
OPT
R293
0.1uF
OPT
C221
0.1uF
OPT
C255
0.1uF
OPT
C223
C-MVREFCA
0.1uF
OPT
C212
0.1uF
OPT
C239
0.1uF
OPT
C207
VCC1.5V_U3_DDR
0.1uF
OPT
C225
+1.5V_FRC_DDR
0.1uF
OPT
C252
10uF
10V
OPT
C267
0.1uF
OPT
C259
0.1uF
OPT
C211
0.1uF
OPT
C265
0.1uF
OPT
C266
0.1uF
OPT
C201
0.1uF
OPT
C238
VCC1.5V_U3_DDR
C-MVREFDQ
0.1uF
OPT
C260
0.1uF
OPT
C264
0.1uF
OPT
C254
1000pF
OPT
C208
1K
1%
OPT
R292
0 . 1 u F
16V
OPT
C268
22
R305
22
R300
22
R303
22
R304
USB2_DP_to_MAIN
USB2_DM_to_MAIN
0
R245
0
R246
LGE101DC-R [S7R DIVX/MS10]
IC101
A_RXCP
F1
A_RXCN
F2
A_RX0P
G2
A_RX0N
G3
A_RX1P
H3
A_RX1N
G1
A_RX2P
H1
A_RX2N
H2
DDCDA_DA/GPIO24
F5
DDCDA_CK/GPIO23
F4
HOTPLUGA/GPIO19
E6
B_RXCP
D3
B_RXCN
C1
B_RX0P
D1
B_RX0N
D2
B_RX1P
E2
B_RX1N
E3
B_RX2P
F3
B_RX2N
E1
DDCDB_DA/GPIO26
D4
DDCDB_CK/GPIO25
E4
HOTPLUGB/GPIO20
D5
C_RXCP
AA2
C_RXCN
AA1
C_RX0P
AB1
C_RX0N
AA3
C_RX1P
AB3
C_RX1N
AB2
C_RX2P
AC2
C_RX2N
AC1
DDCDC_DA/GPIO28
AB4
DDCDC_CK/GPIO27
AA4
HOTPLUGC/GPIO21
AC3
D_RXCP
A2
D_RXCN
A3
D_RX0P
B3
D_RX0N
A1
D_RX1P
B1
D_RX1N
B2
D_RX2P
C2
D_RX2N
C3
DDCDD_DA/GPIO30
B4
DDCDD_CK/GPIO29
C4
HOTPLUGD/GPIO22
E5
CEC/GPIO5
D6
HSYNC0
G5
VSYNC0
G6
RIN0P
K1
RIN0M
L3
GIN0P
K3
GIN0M
K2
BIN0P
J 3
BIN0M
J 2
SOGIN0
J 1
HSYNC1
G4
VSYNC1
H6
RIN1P
K5
RIN1M
K4
GIN1P
J 4
GIN1M
K6
BIN1P
H4
BIN1M
J 6
SOGIN1
J 5
HSYNC2
H5
RIN2P
N3
RIN2M
N2
GIN2P
M2
GIN2M
M1
BIN2P
L2
BIN2M
L1
SOGIN2
M3
CVBS0P
N4
CVBS1P
N6
CVBS2P
L4
CVBS3P
L5
CVBS4P
L6
CVBS5P
M4
CVBS6P
M5
CVBS7P
K7
CVBS_OUT1
M6
CVBS_OUT2
M7
VCOM0
N5
VIFP
W2
VIFM
W1
I P
V2
IM
V1
S S I F / S I F P
Y2
SSIF/SIFM
Y1
QP
U3
QM
V3
IFAGC
Y5
RF_TAGC
Y4
TGPIO0/UPGAIN
U1
TGPIO1/DNGAIN
U2
TGPIO2/I2C_CLK
R3
TGPIO3/I2C_SDA
T3
XTALIN
T2
XTALOUT
T1
SPDIF_IN/GPIO177
G14
SPDIF_OUT/GPIO178
G13
DM_P0
B7
DP_P0
A7
DM_P1
AF17
DP_P1
AE17
I2S_IN_BCK/GPIO175
F14
I2S_IN_SD/GPIO176
F13
I2S_IN_WS/GPIO174
F15
I2S_OUT_BCK/GPIO181
D20
I2S_OUT_MCK/GPIO179
E20
I2S_OUT_SD/GPIO182
D19
I2S_OUT_SD1/GPIO183
F18
I2S_OUT_SD2/GPIO184
E18
I2S_OUT_SD3/GPIO185
D18
I2S_OUT_WS/GPIO180
E19
LINE_IN_0L
N1
LINE_IN_0R
P3
LINE_IN_1L
P1
LINE_IN_1R
P2
LINE_IN_2L
P4
LINE_IN_2R
P5
LINE_IN_3L
R6
LINE_IN_3R
T6
LINE_IN_4L
U5
LINE_IN_4R
V5
LINE_IN_5L
U6
LINE_IN_5R
V6
LINE_OUT_0L
U4
LINE_OUT_2L
W3
LINE_OUT_3L
W4
LINE_OUT_0R
V4
LINE_OUT_2R
Y3
LINE_OUT_3R
W5
MIC_DET_IN
R4
MICCM
T5
MICIN
R5
AUCOM
T4
VRM
P7
VAG
R7
VRP
P6
HP_OUT_1L
R1
HP_OUT_1R
R2
ET_RXD0
E21
ET_TXD0
E22
ET_RXD1
D21
ET_TXD1
F21
ET_REFCLK
E23
ET_TX_EN
D22
ET_MDC
F22
ET_MDIO
D23
ET_CRS
F23
AVLINK
F8
IRINT
G8
TESTPIN
K8
RESET
A4
NC_16
Y17
LGE101DC-R [S7R DIVX/MS10]
IC101
NC_48
AE1
NC_78
AF16
NC_64
AF1
NC_50
AE3
NC_45
AD14
NC_34
AD3
NC_77
AF15
NC_65
AF2
NC_62
AE15
NC_33
AD2
NC_47
AD16
NC_46
AD15
NC_63
AE16
NC_66
AF3
NC_76
AF14
NC_32
AD1
NC_44
AD13
NC_61
AE14
NC_60
AE13
NC_51
AE4
NC_36
AD5
NC_67
AF4
NC_35
AD4
NC_49
AE2
NC_71
AF8
NC_40
AD9
NC_56
AE9
NC_72
AF9
NC_58
AE11
NC_69
AF6
NC_53
AE6
NC_74
AF11
NC_37
AD6
NC_43
AD12
NC_52
AE5
NC_75
AF12
NC_68
AF5
NC_59
AE12
NC_57
AE10
NC_70
AF7
NC_42
AD11
NC_38
AD7
NC_41
AD10
NC_54
AE7
NC_73
AF10
NC_39
AD8
NC_55
AE8
NC_12
Y11
GND_105
Y19
LVACLKP/LLV6P/BLUE[3]
W26
LVACLKN/LLV6N/BLUE[2]
W25
LVA0P/LLV3P/BLUE[9]
U26
LVA0N/LLV3N/BLUE[8]
U25
LVA1P/LLV4P/BLUE[7]
U24
LVA1N/LLV4N/BLUE[6]
V26
LVA2P/LLV5P/BLUE[5]
V25
LVA2N/LLV5N/BLUE[4]
V24
LVA3P/LLV7P/BLUE[1]
W24
LVA3N/LLV7N/BLUE[0]
Y26
LVA4P/LLV8P
Y25
LVA4N/LLV8N
Y24
LVBCLKP/LLV0P/GREEN[5]
AC26
LVBCLKN/LLV0N/GREEN[4]
AC25
LVB0P/RLV6P/RED[1]
AA26
LVB0N/RLV6N/RED[0]
AA25
LVB1P/RLV7P/GREEN[9]
AA24
LVB1N/RLV7N/GREEN[8]
AB26
LVB2P/RLV8P/GREEN[7]
AB25
LVB2N/RLV8N/GREEN[6]
AB24
LVB3P/LLV1P/GREEN[3]
AC24
LVB3N/LLV1N/GREEN[2]
AD26
LVB4P/LLV0P/GREEN[1]
AD25
LVB4N/LLV0N/GREEN[0]
AD24
RLV3P/RED[7]
AD23
RLV3N/RED[6]
AE23
RLV0P/LVSYNC
AE26
RLV0N/LHSYNC
AE25
RLV1N/LCK
AF26
RLV2P/RED[9]
AF25
RLV1P/LDE
AE24
RLV2N/RED[8]
AF24
RLV4P/RED[5]
AF23
RLV4N/RED[4]
AD22
RLV5P/RED[3]
AE22
RLV5N/RED[2]
AF22
TCON3/OE/GOE/GCLK2
AD19
TCON15/SCAN_BLK1
AE19
TCON18/CS7/GCLK5
AD21
TCON19/CS8/GCLK6
AE21
TCON11/CS5/HCON
AF21
TCON10/CS4/OPT_N
AD20
TCON9/CS3/OPT_P
AE20
TCON16/WPWM
AF20
TCON12/DPM
AF19
TCON1/STV/GSP/VST
AD18
TCON5/TP/SOE
AE18
TCON14/SACN_BLK
AF18
TCON21/CS10/VGH_ODD
AB22
TCON20/CS9/VGH_EVEN
AB23
TCON13/LEDON
AC23
TCON17/CS6/GCLK4
AC22
NC_26
AB16
NC_19
AA14
NC_30
AC15
NC_15
Y16
NC_31
AC16
NC_29
AC14
NC_21
AA16
NC_20
AA15
NC_11
Y10
NC_17
AA11
NC_25
AB15
NC_24
AB14
L203
L205
L204
T0X1N
T0X2N
T0X0P
T0X1P
T0XCP
T0X2P
T0X0N
T0XCN
HPD_HDMI
0
R211OPT
0
R213OPT
0
R215OPT
0
R399OPT
4.7K
R302
+3.3V
4.7K
R301
2 1 4
AV IN/LVDS
C l o s e t o I C
a s c l o s e a s p o s s i b l e
* A c t i v e H i g h r e s e t
AUDIO IN
TV/MNT
SERIAL DATA
WORD SELECT
MASTER CLOCK
COMPONENT 1/2
BIT CLOCK
MUST BE LINE IMPEADANCE 100 OHM !!
MINILV
C l o s e t o I C
a s c l o s e a s p o s s i b l e
N/A
CVBS
IIS
DSUB
FRC PART
S7 RESET CIRCUIT
HDMI
CH_5
LVDS OUT
50/60Hz LVDS
FRC
LOW
U 3 _ I N T E R N A L : H I G H L O W
GIP
PIN NO.
F7
MODEL_OPT_6
DDR_256MB
MINI LVDS
U 3 _ E X T E R N A L : H I G H H I G H
NON_GIP
HD
HIGH
LVDS
PIN NAME
F9
PWIZ TCON with LG FRC : HIGH HIGH
D18
G19
MODEL_OPT_3
OPT_4
FHD
MODEL_OPT_1
NO FRC
MODEL_OPT_2
B6
MODEL_OPT_4
LCD
OPT_0
100/120Hz LVDS
DDR_512MB
MODEL OPTION
MODEL_OPT_0
N O _ F R C : L O W L O W
E18
OLED
MODEL_OPT_5
C5
MODEL OPTION
3 ’ d 5 : b o o t f r o m i n t e r n a l S R A M
3 ’ d 6 : b o o t f r o m E E P R O M
3 ’ d 7 : b o o t f o r m S P I f l a s h
HIGH : I2C ADR = B8
LOW : I2C ADR = B4
(FRC_CONF0)
(FRC_CONF1,FRC_PWM1, FRC_PWM0)
<U3 CHIP Config>
Close to DDR Power Pin
C L o s e t o S a t u r n 7 M I C
DDR3 1.5V By CAP - Place these Caps near Memory
CLose to DDR3
P l a c e 2 2 o h m a t S 7
MUST BE LINE IMPEADANCE 100 OHM !!
1 1 / 0 5 / 1 1
EAX64050803
Copyright ⓒ 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 47WV30BS
Page 36: ......