LG 47WV30BS, Service Manual, Page: 26 / 36

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
1K
1%
R1225
10
R1208
B-MODT
B-TMA8
10
AR1220
A-TMA4
0.1uF
C1245
A-TMA1
A-MDML
B-TMCASB
A-MDQL0
A-TMDQU4
A-TMRASB
B-MDQL5
B-MDQL7
A-MDQL2
B-TMA6
VCC_1.5V_DDR
B-MA5
A-MA6
0.1uF
C1215
B-MCKE
B-MRASB
B-MDQL0
0.1uF
C1214
A-MA12
VCC_1.5V_DDR
10
R1206
B-MDQU0
B-TMA7
B-MA6
10
AR1211
A-MRASB
B-MA1
A-TMBA0
B-TMODT
B-MWEB
B-MCKE
10
AR1201
B-TMDQU4
A-MA6
B-TMCKB
B-TMDQU1
B-MCASB
A-TMCASB
B-MBA1
A-TMA3
10
R1209
A-TMDQL3
0.1uF
C1243
A-MDQL6
0.1uF
C1230
B-TMDQL6
B-MA8
10
AR1205
B-MDQU1
A-MDQL1
B-MA5
0.1uF
C1208
A-TMCK
B-MA9
B-TMDQSLB
0.1uF C1235
A-TMDQU2
B-MDQSU
B-TMA13
A-MDQU0
0.1uF
C1248
A-TMDQU7
0.1uF
C1237
A-TMDQSLB
B-MDQL4
0.1uF
C1244
A-MA11
B-MDQL0
A-MA4
A-TMA6
A-TMA8
A-MVREFDQ
240
1%
R1203
B-TMDQL7
B-MCASB
B-MVREFCA
B-TMCK
10
R1213
A-MRESETB
0.1uF
C1241
B-TMRESETB
0.1uF
C1231
A-TMBA2
A-TMA12
A-MDQU6
10
AR1214
10
AR1209
0.1uF
C1233
B-TMDQSLB
A-MA9
A-MCKE
A-TMCK
B-MA11
B-TMA9
A-TMDQU2
A-MDQL4
B-MA2
A-MDQL4
B-TMDQU7
10
AR1212
B-MA0
10
AR1207
A-TMDQL0
A-MDQL7
B-TMDQU7
A-MDQSL
10
R1223
A-MDQU7
B-MA0
0.1uF
C1210
A-TMDQU1
A-MDQSLB
B-MDQL5
A-TMODT
B-TMDQSUB
B-TMA13
0.1uF C1216 0.1uF
C1222 10uF C1246
B-MDQL2
10
R1210
A-TMDQU5
A-MDQU0
A-MODT
A-MBA0
A-TMDQL2
A-MDQU1
B-MA2
A-MDQL6
1000pF
C1204
B-MA13
0.1uF
C1227
0.1uF
C1203
10
R1222
B-TMDQL5
A-MA12
B-MDQU5
B-TMDQL4
240
1%
R1226
0.1uF
C1234
A-MWEB
A-MDQSL
B-TMCK
10
AR1210
10
AR1203
A-MDQU3
B-MA6
B-MDQL1
A-TMRASB
B-TMA8
B-MCK
A-MDMU
0.1uF
C1211
A-TMDQU0
A-TMBA1
A-MA0
B-MDQU4
A-MA1
1K
1%
R1205
0.1uF
C1238
0.1uF
C1223
A-TMDQSL
B-TMBA2
B-MA7
A-TMA11
B-MA10
A-MDML
B-TMA9
B-TMBA0 B-MBA0
A-MA10
A-MDQU4 B-TMDQU3
A-MA8
B-TMDQL1
VCC_1.5V_DDR
A-TMDQL2
B-TMCKE
B-MVREFDQ
A-MVREFDQ
A-TMBA0
1000pF
C1249
A-TMDQU6
A-TMRESETB
10K
R1232
1K
1%
R1227
B-MA12
10
R1220
A-MA11
A-MA7
A-TMDML
0.1uF
C1217
B-MDMU
1K
1%
R1228
A-MDQSUB
A-MA5
B-MDQU0
10uF C1205
VCC_1.5V_DDR
B-TMA1
A-MDQU3
10K
R1231
A-TMDMU
B-MRASB
B-MDQL3
0.1uF
C1207
A-TMA0
B-TMBA1
B-TMRASB
A-MDQL5
A-TMA13
A-TMCKB
B-TMDQU2
0.1uF
C1219
A-TMDQL7
B-TMCASB
A-MBA2
B-MBA1
B-TMWEB
A-TMWEB
B-MA8
B-TMA10
B-TMA12
A-TMDQU6
A-MBA1
A-TMDQL6
A-TMDQL1
A-TMDQU3
B-MDQL7
1K
1%
R1202
A-MWEB
B-TMRESETB
B-MA12
10
AR1219
B-MDQSU
10
AR1204
A-TMDQL3
B-MDQSUB
B-TMDQU0
A-MDQL7
A-MA4
A-TMA12
B-MA7
A-MDQSU
10
AR1213
A-MDQU5
B-MA13
B-MBA0
A-MDQL2
A-TMA7
0.1uF
C1228
B-TMDQU2
B-MDQSL
B-TMA11
B-MDQL3
A-MCKB
B-MA1
1000pF
C1202
A-TMCASB
A-MDQU2
A-TMA7
A-TMA9
B-TMODT
A-TMA5
A-MDQL5
A-MDQU2
A-MA2
1K
1%
R1201
B-MDQU3
B-MDQU4
B-TMA12
B-TMCKB
A-TMA1
B-MA11
0.1uF
C1224
B-MDQU3
B-MDQU2
L1201
A-TMBA1
A-MRASB
B-TMDML
A-MA2
A-TMCKE
0.1uF
C1218
B-TMDQU0
VCC_1.5V_DDR
VCC_1.5V_DDR
10
R1218
A-TMDQU4
B-MA10
A-MDQU4
10
R1221
A-MDQL0
A-TMDQL6
A-MBA0
+1.5V_DDR_IN
A-TMDQU7
B-TMDQU1
A-MDQU6
A-MDQU1
B-TMA7
10
R1212
B-TMDML
B-MDML
0.1uF
C1220
A-TMDQL5
A-MA13
B-MVREFDQ
B-TMDQL4
A-MVREFCA
B-MWEB
A-TMDQSU
B-MDQSL
B-TMA4
0.1uF
C1212
10
R1207
B-MDQU7
A-TMA0
B-MDQL6
B-TMDQU3
A-TMDQSUB
10
R1215
B-MA4
0.1uF
C1232
B-TMBA0
A-MODT
A-MA3
A-MCK
A-TMDQL5
B-TMDQL3
B-MCKB
A-MCKB
B-MA9
B-TMA3
B-TMA2
VCC_1.5V_DDR
A-MA5
10
R1211
A-MA13
A-MCASB
B-TMDQU6
A-TMA2
B-TMCKE
0.1uF
C1250
A-TMDQL4
B-TMDQL2
A-MDMU
B-MBA2
A-TMDQL4
B-TMA5
B-TMDMU
VCC_1.5V_DDR
VCC_1.5V_DDR
10
R1217
10
AR1206
A-MA1
B-MRESETB
B-MDQL2
10
AR1202
A-TMDQL7
A-TMRESETB
B-MDMU
A-TMA6
B-MDQU1
A-TMDQU5
B-MDQU5
1K
1%
R1224
B-TMA0
0.1uF
C1206
VCC_1.5V_DDR
B-TMDQU5
A-MDQU5
A-TMA13
B-TMDQU5
A-MBA1
B-TMBA2
B-TMA4
B-TMA2
B-TMDQL0
B-MDQSLB
B-MRESETB
0.1uF
C1201
B-TMWEB
A-TMA11
0.1uF
C1229
A-TMA3
B-TMDQU4
A-MVREFCA
A-TMCKB
10
AR1208
10
AR1217
B-MDQU2
1K
1%
R1204
A-MDQSU
0 . 1 u F
16V
C1226
0.1uF
C1239
10
AR1218
B-TMDQL5
B-TMA11
A-TMA5
A-TMDQL0
B-TMDQL3
B-MDQU7
A-MA10
VCC_1.5V_DDR
B-MBA2
A-MDQSUB
A-MCASB
A-TMDQSU
A-TMBA2
B-TMDQSU
A-MDQL3
B-TMBA1
B-MA4
A-TMDMU
B-TMDQL6
A-TMDML
A-TMWEB
A-TMA10
B-MDQU6
A-TMDQSUB
1000pF
C1247
B-TMDQSUB
A-TMA2
A-TMDQU3
10
R1214
A-MDQL1
B-TMRASB
A-TMODT
A-MA7
A-TMDQSL
A-MA3
B-MODT
A-MRESETB
A-MCKE
B-MCK
A-MDQU7
A-MCK
0.1uF
C1236
A-TMA4
A-TMDQL1
B-MDQSUB
B-MDQU6
B-MDML
B-MDQL1
B-TMDMU
B-TMA10
A-MA0
B-TMA6
A-MBA2
B-MDQL6
10
AR1215
0.1uF
C1213
B-MVREFCA
B-MDQL4
10uF
10V
C1225
B-MDQSLB
B-TMDQSL
B-TMDQU6
A-TMA10
A-TMDQSLB
B-TMDQL7
B-TMA0
B-TMA1
B-MA3
B-TMA5
A-TMA9
A-MDQSLB
A-MDQL3
B-MCKB
0.1uF
C1221
B-TMDQSU
0.1uF
C1242
A-MA8
10
R1219
A-MA9
B-TMDQL2
B-TMDQSL
B-TMA3
A-TMDQU1
B-TMDQL0
B-TMDQL1
10
R1216
10
AR1216
A-TMA8
B-MA3
A-TMCKE
A-TMDQU0
B-MCKE
10K R1234
10K R1233
A-MCKE
56
R1236
0 . 0 1 u F
C1209
56
R1235
56
R1238
0 . 0 1 u F
C1240 56
R1237
LGE101DC-R [S7R DIVX/MS10]
IC101
A_DDR3_A0/DDR2_A13
B8
A_DDR3_A1/DDR2_A8
B9
A_DDR3_A2/DDR2_A9
A8
A_DDR3_A3/DDR2_A1
C21
A_DDR3_A4/DDR2_A2
B10
A_DDR3_A5/DDR2_A10
A22
A_DDR3_A6/DDR2_A4
A10
A_DDR3_A7/DDR2_A3
B22
A_DDR3_A8/DDR2_A6
C9
A_DDR3_A9/DDR2_A12
C23
A_DDR3_A10/DDR2_RASZ
B11
A_DDR3_A11/DDR2_A11
A9
A_DDR3_A12/DDR2_A0
C10
A_DDR3_A13/DDR2_A7
B23
A_DDR3_BA0/DDR2_BA2
B21
A_DDR3_BA1/DDR2_CASZ
A11
A_DDR3_BA2/DDR2_A5
A23
A_DDR3_MCLK/DDR2_MCLK
A12
A_DDR3_MCLKZ/DDR2_MCLKZ
C11
A_DDR3_CKE/DDR2_DQ5
B12
A_DDR3_ODT/DDR2_ODT
C20
A_DDR3_RASZ/DDR2_WEZ
A20
A_DDR3_CASZ/DDR2_BA1
B20
A_DDR3_WEZ/DDR2_BA0
A21
A_DDR3_RESETB
C22
A_DDR3_DQSL/DDR2_DQS0
C16
A_DDR3_DQSLB/DDR2_DQSB0
B16
A_DDR3_DQSU/DDR2_DQSB1
A16
A_DDR3_DQSUB/DDR2_DQS1
C15
A_DDR3_DML//DDR2_DQ13
A14
A_DDR3_DMU/DDR2_DQ6
B18
A_DDR3_DQL0/DDR2_DQ3
C18
A_DDR3_DQL1/DDR2_DQ7
B13
A_DDR3_DQL2/DDR2_DQ1
A19
A_DDR3_DQL3/DDR2_DQ10
C13
A_DDR3_DQL4/DDR2_DQ4
C19
A_DDR3_DQL5/DDR2_DQ0
A13
A_DDR3_DQL6/DDR2_CKE
B19
A_DDR3_DQL7/DDR2_DQ2
C12
A_DDR3_DQU0/DDR2_DQ15
A15
A_DDR3_DQU1/DDR2_DQ9
A17
A_DDR3_DQU2/DDR2_DQ8
B14
A_DDR3_DQU3/DDR2_DQ11
C17
A_DDR3_DQU4/DDR2_DQM1
B15
A_DDR3_DQU5/DDR2_DQ12
A18
A_DDR3_DQU6/DDR2_DQM0
C14
A_DDR3_DQU7/DDR2_DQ14
B17
B_DDR3_A0/DDR2_A13
A25
B_DDR3_A1/DDR2_A8
B24
B_DDR3_A2/DDR2_A9
A24
B_DDR3_A3/DDR2_A1
P25
B_DDR3_A4/DDR2_A2
C24
B_DDR3_A5/DDR2_A10
P26
B_DDR3_A6/DDR2_A4
B26
B_DDR3_A7/DDR2_A3
R24
B_DDR3_A8/DDR2_A6
B25
B_DDR3_A9/DDR2_A12
T26
B_DDR3_A10/DDR2_RASZ
D24
B_DDR3_A11/DDR2_A11
A26
B_DDR3_A12/DDR2_A0
C25
B_DDR3_A13/DDR2_A7
T25
B_DDR3_BA0/DDR2_BA2
P24
B_DDR3_BA1/DDR2_CASZ
C26
B_DDR3_BA2/DDR2_A5
R26
B_DDR3_MCLK/DDR2_MCLK
D26
B_DDR3_MCLKZ/DDR2_MCLKZ
D25
B_DDR3_CKE/DDR2_DQ5
E24
B_DDR3_ODT/DDR2_ODT
N25
B_DDR3_RASZ/DDR2_WEZ
M26
B_DDR3_CASZ/DDR2_BA1
N24
B_DDR3_WEZ/DDR2_BA0
N26
B_DDR3_RESETB
R25
B_DDR3_DQSL/DDR2_DQS0
J 2 5
B_DDR3_DQSLB/DDR2_DQSB0
J 2 4
B_DDR3_DQSU/DDR2_DQSB1
H26
B_DDR3_DQSUB/DDR2_DQS1
H25
B_DDR3_DML/DDR2_DQ13
F26
B_DDR3_DMU/DDR2_DQ6
L24
B_DDR3_DQL0/DDR2_DQ3
L25
B_DDR3_DQL1/DDR2_DQ7
F24
B_DDR3_DQL2/DDR2_DQ1
L26
B_DDR3_DQL3/DDR2_DQ10
F25
B_DDR3_DQL4/DDR2_DQ4
M25
B_DDR3_DQL5/DDR2_DQ0
E26
B_DDR3_DQL6/DDR2_CKE
M24
B_DDR3_DQL7/DDR2_DQ2
E25
B_DDR3_DQU0/DDR2_DQ15
G26
B_DDR3_DQU1/DDR2_DQ9
J 2 6
B_DDR3_DQU2/DDR2_DQ8
G24
B_DDR3_DQU3/DDR2_DQ11
K25
B_DDR3_DQU4/DDR2_DQM1
H24
B_DDR3_DQU5/DDR2_DQ12
K26
B_DDR3_DQU6/DDR2_DQM0
G25
B_DDR3_DQU7/DDR2_DQ14
K24
H5TQ1G63DFR-H9C
IC1201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ1G63DFR-H9C
IC1202
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
1 2 1 4
DDR
C L o s e t o S a t u r n 7 M I C
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
C L o s e t o S a t u r n 7 M I C
CLose to DDR3
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
CLose to DDR3
1 1 / 0 5 / 1 1
EAX64050803
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Only for training and service purposes LGE Internal Use Only