THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
15/04/27
MAIN4_EXT_IN/OUTPUT
04
K2L
L600
PZ1608U121-2R0TF
C634
0.047uF
DTV/MNT_V_OUT
COMP1_YPbPrN
TXDBP1_L
I2C_SDA6
MCLK_A
HP_ROUT
BIT9
COMP1_YPbPrN
TXDAN1_L
BIT8
C630
0.047uF
R610
100
TXDBP6_L
TU_CVBS
L601
PZ1608U121-2R0TF
SC_CVBS_IN
C656
1uF
C603
5pF
50V
TXDBN2_L
BIT0
GST_A
DTV/MNT_V_OUT
TXDAP1_L
L/D_CLK
COMP1_Y/CVBS
R611
100
TXDBN7_L
GST_A
COMP1_YPbPrN
COMP1_PbP
TXDBP2_L
LOCKAn
TXDBN4_L
COMP1_Y/CVBSP
TXDAN2_L
L/D_DO
C629
0.047uF
R614
100
TXDBP7_L
MCLK_A
C632
0.047uF
C657
0.1uF
16V
SC_CVBS_IN
TXDBN3_L
HTPDAn
TXDBP4_L
COMP1_PbP
TXDAP2_L
L/D_VSYNC
COMP1_Pb
R612
100
COMP1_PrP
TXDBN0_L
EO_A
COMP1/AV1/DVI_R_IN
VID_CORE
TXDBP3_L
BIT5
TXDBN5_L
COMP1_PrP
TXDAN3_L
DATA_FORMAT_0
C631
0.047uF
R613
100
COMP1_YPbPrN
TXDBP0_L
GCLK_A
COMP1/AV1/DVI_L_IN
VID_CPU
COMP1_Y/CVBSP
TXDAN0_L
BIT6
GCLK_A
TXDBP5_L
C635
0.047uF
TXDAP3_L
DATA_FORMAT_1
COMP1_Pr
C605
5pF
50V
TXDBN1_L
I2C_SCL6
EO_A
HP_LOUT
AMP_RESET_N
C604
5pF
50V
TXDAP0_L
BIT7
R615
100
TXDBN6_L
C606
5pF
50V
C633
0.047uF
C655
2.2uF
C654
2.2uF
TXDAN2_L
TXDAP2_L
TXDAN3_L
TXDAP3_L
TXDAN1_L
TXDAP1_L
TXDAP0_L
TXDAN0_L
VX1_MSE
AGP_CTRL
IC100
LGE6551-CA1
LVDS_AAN
B25
LVDS_AAP
A25
LVDS_ABN
B24
LVDS_ABP
A24
LVDS_ACN
B23
LVDS_ACP
A23
LVDS_ADN
B22
LVDS_ADP
A22
LVDS_AEN
B21
LVDS_AEP
A21
LVDS_AFN
B20
LVDS_AFP
A20
LVDS_BAN
AF28
LVDS_BAP
AF27
LVDS_BBN
AG28
LVDS_BBP
AG27
LVDS_BCN
AH28
LVDS_BCP
AH27
LVDS_BDN
AJ28
LVDS_BDP
AJ27
LVDS_BEN
B27
LVDS_BEP
A27
LVDS_BFN
B26
LVDS_BFP
A26
LVDS_CAN
B29
LVDS_CAP
A29
LVDS_CBN
B28
LVDS_CBP
A28
LVDS_CCN
AJ30
LVDS_CCP
AJ29
LVDS_CDN
AK31
LVDS_CDP
AK30
LVDS_CEN
AL31
LVDS_CEP
AK29
LVDS_CFN
AL30
LVDS_CFP
AL29
LVDS_DAN
AF31
LVDS_DAP
AF30
LVDS_DBN
AF29
LVDS_DBP
AG30
LVDS_DCN
AG29
LVDS_DCP
AH31
LVDS_DDN
AH30
LVDS_DDP
AH29
LVDS_DEN
B31
LVDS_DEP
A31
LVDS_DFN
B30
LVDS_DFP
A30
IC100
LGE6551-CA1
VINRP
C1
VINRN
D1
VINGP
B1
VINGN
C2
VINBP
A1
VINBN
C3
VSYNC
B2
HSYNC
A2
VIN3P
D2
VIN4P
E2
VIN5P
E3
VINY0N
D3
VIN10P
F3
VIN13P
F1
VINA0N
F2
AI1L
A4
AI1R
B4
AI2L
A5
AI2R
B5
AI4L
D4
AI4R
D5
AIO2L
E4
AIO2R
E5
HPOL
F4
HPOR
F5
VDACOUT
G2
FSW0
G3
SPDIF_OUT
C5
MICBAIS
C4
ADCG
AB5
BBG
AG5
VCMBB
AF5
EPI Share Lane
For 51p location
GND pattern should be
connected with 75ohm reg
of Component Jack
EPI Lane
For 41p location
GND pattern should be
connected with 75ohm reg
of SCART Jack
EPI Share Lane
For 41p location
Close to Main chip
EPI Lane
For 41p location
Level Shifter
port changed
(SPDIF noise issue)
Level Shifter
Internal Analog Demod Test Point
Default Low Set!
Copyright © 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 43UH610
Page 59: ......