THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M0_DDR_DQS_N0
R428
1K
1%
M0_DDR_DQ26
M0_DDR_DM2
C436
0.1uF
16V
M0_DDR_BA2
M0_DDR_DQ7
M0_CS1_N
M0_DDR_A3
M0_DDR_DQ2
M0_DDR_A1
M0_DDR_DM0
M0_DDR_DQS2
M0_DDR_A5_1
M0_DDR_A5
C434
0.1uF
16V
M0_DDR_A0
M0_DDR_A3
M0_DDR_A4_1
M0_DDR_DQ21
M0_DDR_DQ26
M0_DDR_DQ24
C407
0.1uF
16V
+1.5V_DDR
R402
1K
1%
M0_DDR_DQS3
R410
1K
1%
C413
0.1uF
M0_DDR_WEN
+1.5V_DDR
M0_DDR_A4
M0_DDR_DQ15
M0_DDR_A5_1
M0_DDR_DQS0
M0_DDR_DQ11
M0_DDR_DQ31
M0_DDR_VREFDQ
M0_DDR_A12
R403
1K
1%
M0_DDR_DQS_N1
M0_DDR_DQ31
M0_DDR_VREFDQ
R416
0
M0_DDR_A6
M0_DDR_DQ5
M0_CS0_N
M0_DDR_DQ9
M0_DDR_DQ1
M0_DDR_DQ14
M0_DDR_DQ13
+1.5V_DDR
M0_DDR_DQS1
C405
0.1uF
16V
C417
0.1uF
M0_DDR_DQ20
R417
0
M0_DDR_BA0
M0_DDR_DQ24
M0_CS1_N
R439
240
1%
M0_DDR_DQ3
C416
0.1uF
R451
120
1%
VREF_M1
M0_DDR_DM3
R429
1K
1%
M0_DDR_A14
M0_CS0_N
R405
1K
1%
M0_DDR_A7
M0_DDR_A2
M0_CS0_N
M0_DDR_A8
M0_DDR_DQ15
M0_DDR_DQS_N1
R450
120
1%
M0_DDR_A13
M0_DDR_DM0
+1.5V_DDR
M0_DDR_ODT
VREF_M1
M0_DDR_ODT
M0_DDR_A8
M0_CS1_N
M0_DDR_RASN
M0_DDR_DQ20
M0_DDR_CKE
M0_DDR_DQS_N3
M0_DDR_RASN
M0_DDR_DM1
M0_DDR_A4
M0_DDR_A13
C419
0.1uF
16V
M0_DDR_CASN
C412
0.1uF
R446
120
1%
M0_DDR_DM1
M0_DDR_DQ18
R409
1K
1%
M0_DDR_A0
M0_DDR_A11
M0_DDR_DM2
M0_1_DDR_VREFCA
M0_DDR_A6
R404
1K
1%
M0_DDR_A9
M0_DDR_BA1
R447
120
1%
M0_DDR_DQ19
M0_DDR_DQ29
R426
1K
M0_DDR_A10
M0_CS0_N
VREF_M0
+1.5V_DDR
M0_DDR_A8
M0_DDR_DQ22
M0_DDR_BA0
M0_U_CLKN
M0_DDR_DQ5
M0_1_DDR_VREFCA
M0_DDR_DQ16
C431
0.1uF
16V
M0_DDR_A14
R400
240
1%
M0_1_DDR_VREFDQ
M0_DDR_BA1
M0_DDR_A13
M0_DDR_DQ18
M0_DDR_DQS_N0
M0_DDR_DQ8
R424
1K
1%
M0_U_CLKN
M0_DDR_A12
M0_DDR_RESET_N
+1.5V_DDR_INSTANTBOOT
M0_DDR_DQ6
M0_DDR_DQ11
M0_DDR_A1
M0_DDR_DQ6
M0_DDR_DQ19
M0_DDR_VREFCA
M0_DDR_DM3
+1.5V_DDR
M0_DDR_CKE
+1.5V_DDR
M0_DDR_CASN
+1.5V_DDR
M0_DDR_DQ25
M0_DDR_ODT
M0_DDR_DQ2
M0_DDR_RASN
M0_DDR_DQ7
+1.5V_DDR
M0_DDR_A6
C426
0.1uF
16V
M0_DDR_RESET_N
M0_U_CLKN
M0_DDR_DQS2
R423
0
OPT
M0_DDR_DQ13
M0_U_CLK
M0_DDR_DQ0
M0_DDR_A2
M0_DDR_DQ17
R407
1K
1%
M0_DDR_BA0
M0_DDR_DQ30
M0_DDR_A10
M0_CLKN
M0_DDR_A10
R422
0
OPT
M0_DDR_DQ28
+1.5V_DDR
M0_DDR_A7
M0_DDR_DQ22
C404
0.1uF
16V
M0_DDR_CASN
M0_DDR_DQ3
C424
0.1uF
16V
M0_CLKN
M0_CLK
M0_DDR_A9
M0_DDR_DQ4
M0_DDR_CKE
M0_DDR_A9
M0_DDR_A12
M0_DDR_DQ16
+1.5V_DDR
M0_DDR_DQ14
C425
0.1uF
16V
M0_DDR_A1
M0_U_CLK
M0_DDR_DQS_N2
H5TQ4G63CFR-TEC
IC401
DDR_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_DDR_DQ27
M0_DDR_WEN
M0_DDR_A14
R443
240
1%
M0_DDR_DQ30
M0_CS1_N
M0_DDR_DQS1
C429
0.1uF
16V
M0_DDR_WEN
C400
0.1uF
16V
M0_DDR_A0
H5TQ4G63CFR-TEC
IC403
DDR_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_DDR_DQ12
M0_DDR_BA2
M0_DDR_DQ27
M0_DDR_A11
M0_DDR_DQ10
+1.5V_DDR
M0_DDR_DQ4
M0_DDR_DQ28
C428
0.1uF
16V
M0_DDR_A3
C402
0.1uF
16V
M0_DDR_DQ10
C438 0.1uF
16V
M0_DDR_DQ23
M0_DDR_DQS3
M0_DDR_DQ29
+1.5V_DDR
M0_DDR_DQ17
M0_DDR_DQS_N2
R408
1K
1%
R436
1K
M0_DDR_DQ12
C427
0.1uF
16V
M0_DDR_A5
C401
0.1uF
16V
M0_DDR_DQ23
M0_DDR_DQ0
M0_DDR_A11
M0_DDR_BA1
M0_DDR_RESET_N
M0_DDR_DQS0
R425
1K
1%
+1.5V_DDR
M0_DDR_VREFCA
C432
0.1uF
16V
M0_CLK
C403
0.1uF
16V
M0_DDR_DQ1
M0_DDR_DQ21
M0_DDR_DQ8
M0_DDR_A4_1
R401
240
1%
M0_DDR_A7
M0_DDR_DQS_N3
M0_1_DDR_VREFDQ
M0_DDR_BA2
M0_DDR_A2
M0_DDR_CKE
C418
0.1uF
16V
C440 0.1uF
16V
M0_DDR_DQ9
M0_U_CLK
M0_DDR_DQ25
VREF_M0
R420
27
R421
27
C441
10uF
10V
C442
10uF
10V
C443
10uF
10V
C444
10uF
10V
IC100
LGE6551-CA1
DC1_A0
G28
DC1_A1
J31
DC1_A2
F30
DC1_A3
E28
DC1_A4
L28
DC1_A5
F27
DC1_A6
K27
DC1_A7
F28
DC1_A8
J28
DC1_A9
G31
DC1_A10
M27
DC1_A11
H28
DC1_A12
L27
DC1_A13
G30
DC1_A14
J30
DC1_A15
L31
DC1_A4_EXT
K29
DC1_A5_EXT
G27
DC1_BA0
E27
DC1_BA1
K30
DC1_BA2
H27
DC1_CASN
H30
DC1_CKE
M28
DC1_CLK
M30
DC1_CLKB
L30
DC1_CSN
M29
DC1_CSN_1
AD26
DC1_ODT
E30
DC1_RASN
J27
DC1_RST
F29
DC1_WEN
H29
DC1_DQ0
U31
DC1_DQ1
P29
DC1_DQ2
U30
DC1_DQ3
R30
DC1_DQ4
T29
DC1_DQ5
P30
DC1_DQ6
T30
DC1_DQ7
R31
DC1_DQ8
N28
DC1_DQ9
U28
DC1_DQ10
N27
DC1_DQ11
U27
DC1_DQ12
P27
DC1_DQ13
T27
DC1_DQ14
P28
DC1_DQ15
T28
DC1_DQ16
AC31
DC1_DQ17
Y29
DC1_DQ18
AC30
DC1_DQ19
AA30
DC1_DQ20
AB29
DC1_DQ21
Y30
DC1_DQ22
AB30
DC1_DQ23
AA31
DC1_DQ24
W28
DC1_DQ25
AC28
DC1_DQ26
W27
DC1_DQ27
AC27
DC1_DQ28
Y27
DC1_DQ29
AB27
DC1_DQ30
Y28
DC1_DQ31
AB28
DC1_DQS0
V30
DC1_DQS0B
V29
DC1_DQS1
R27
DC1_DQS1B
R28
DC1_DQS2
AD30
DC1_DQS2B
AD29
DC1_DQS3
AA27
DC1_DQS3B
AA28
DC1_DM0
N30
DC1_DM1
U26
DC1_DM2
W30
DC1_DM3
AD27
DDR1_ZQ
D30
DC1_VREF
D31
DDR_1V5_1
A18
DDR_1V5_2
A19
DDR_1V5_3
B18
DDR_1V5_4
B19
DDR_1V5_5
C18
DDR_1V5_6
C19
DDR_1V5_7
D18
DDR_1V5_8
D19
DDR_1V5_9
N19
DDR_1V5_10
N20
DDR_1V5_11
N21
DDR_1V5_12
N22
DDR_1V5_13
N23
DDR_1V5_14
N24
DDR_1V5_15
P24
DDR_1V5_16
R24
DDR_1V5_17
T24
DDR_1V5_18
U24
DDR_1V5_19
V24
DDR_1V5_20
W24
DDR_1V5_21
Y24
DDR2_ZQ
D28
DC2_VREF
D27
MT41K256M16LY-093:N
IC401-*1
DDR_MICRON
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
LDM
E7
UDM
D3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
MT41K256M16LY-093:N
IC403-*1
DDR_MICRON
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
LDM
E7
UDM
D3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
2015-04-27
K2L DDR
K2L
03
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
Place M0 POWER PLANE
Place Near SoC
Place M0 POWER PLANE
Copyright © 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 43UH610
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