LeCroy WAVERUNNER 6000 SERIES, Service Manual

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from 100ns to about 70s with 2ns resolution
(clock reference at 500 MHz)
4.6.1.5.2.8
Trigger Frequency
– Main trigger frequency
up to 750 MHz, Qualifier frequency up to 500
MHz
4.6.2 ADC & Memory -
The ADC function is performed by a two dual channel 5
GS/s, 8 Bit ADC hybrids (HAD639) with 24 Megabytes of DRAM. They have an
8b/10b data link to transfer data to an off board processor. For each pair of
channels (1&2 and 3&4) there is an 8 Bit Hybrid ADC and three 8 Megabyte
DRAM IC’s (MAM439). The ADC can be used either as a dual acquisition
channel, or it may be used as part or a two channel system to interleave data to
achieve a 10GS/s sampling rate
ƒ Controlled via JTAG
ƒ ADCs sample at 5GS/s for 4CH and 10GS/s when Interleaved to 2CH
ƒ Digitized Data Decimated to achieve other sample rates
ƒ Digitized data stored in MAMs and read out over 8b/10b bus
ƒ Gain, Offset and Delay Dacs
ƒ PRBS Generator
10 GHz
Clock Input
MAM
X
Y
RX
TX
MAM
X
Y
RX
TX
MAM
X
Y
RX
TX
2GHz CLK_Input
ADC
Output Port 1
Output Port 4
Output Port 2
Output Port 5
Output Port 3
Output Port 6
9 bit Digital Output Data
1.67GS/s
Differential LVDS Signal
From:
Control FPGA
TTL 8B/10B Data
EXT or
Unused
CH2 or CH4
CH1 or CH3
To:
Control FPGA (2 ch unit)
Ch 3 & 4 MAM (4 ch unit)
Figure 4-7 ADC and Memory Block Diagram
4.6.2.1
HAD639
– 10 GS/s, 8 Bit ADC
4.6.2.1.1
Signal I/O
– The HAD639 has three differential analog inputs
and six output ports that each have nine differential output
signals and two differential quadrature clock outputs.
4.6.2.1.2
ADC’s
– There are six 8 bit ADC’s in this device. Each ADC
operates at a clock speed of 1.667 GHz.
4.6.2.1.3
Calibration
– There are several DAC’s built into the HAD639
to calibrate its ADC’s. For each ADC there are five internal
DAC’s, one for gain, one for offset, one for delay, one for
output delay and one for sample delay.
Theory of Operation
4-11