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1881M

Installation

3-3

July 23, 1998

flowing out of the board may be added (using a very large resistor to a negative supply) to cure the non-
linearity problem, but this will simply move the pedestals and will not affect the magnitude of the rate
shift. Experiments with a distinct time structure to their spill (in the tens of milli-second domain) should
consider this more seriously as they may get a pedestal shift during each spill. To calculate this effect
simply calculate the mean current during the spill. The pedestal could be expected to ramp down during
the spill if the rate is high enough. It should be noted that the guarantee of 8192 codes above intrinsic
pedestal does not mean that that an arbitrary user pedestal can be accommodated without loss of dynamic
range.

Permanently installed jumpers:

•

JL - (upper right hand corner) should be positioned between pins 2, 3 (upper two pins)

•

JU - (upper right hand corner) should be positioned between pins 1, 2 (right two pins)

•

J5 - (middle) should be positioned between pins 2, 3 (left two pins)

Options:

•

J26,J27 - (Lower right hand corner) when inserted CLR input is terminated in 102

Ω

. To bus

CLR remove links from all but the last board on the cable.

•

J24,J25 - (Lower right hand corner) When inserted GATE input is terminated in 102

Ω

s. To

bus GATE remove links from all but the last board on the cable.

•

J5S, J5T, J5V, J5W -(along right edge) When inserted termination is to ground. When

removed termination is allowed to float with 20

µ

F to ground in parallel with 1K. The termination is

shared for entire groups of 16 channels.

•

J2/4S, J2/4T, J2/4V, J2/4W - (along right edge) When 18 pin jumper links are inserted

positive input termination resistors are shorted giving a single ended 51

Ω

input.

•

J1/6S, J1/6T, J1/6V, J1/6W - (along right edge) Storage location for 18 pin links. Links

should be stored here when 102

Ω

differential inputs are desired.

The following list indicates the normal link combinations:

•

51

Ω

single ended (coax) fixed ground (default) - J5 (S,T,V,W) and J2/4 (S,T,V,W) inserted

(J1/6 (S,T,V,W) removed)

•

51

Ω

floating ground - J2/4 (S,T,V,W) inserted (J1/6 (S,T,V,W) and J5 (S,T,V,W)

removed)

•

102

Ω

quasi-differential (twisted pair)- J1/6 (S,T,V,W) and J5 (S,T,V,W) inserted (J2/4

(S,T,V,W) removed)

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Summary of Contents for 1881M

Page 1: ...MODEL 1881M 64 CHANNEL FASTBUS ADC ...

Page 2: ...TBUS specification Specifications The information contained in this manual is subject to change without notice The reference for product specification is the Technical Data Sheet effective at the time of purchase Electrostatic Sensitivity While measures have been taken to protect the MTD133 ASIC from electrostatic damage it is still imperative to follow anti static procedures when handling this CM...

Page 3: ......

Page 4: ...egister 7 2 7 2 5 6 Control and Status Register 16 2 7 2 5 7 Control and Status Register C000000 h C000003F h 2 8 2 6 FASTBUS Operations 2 8 2 6 1 FASTBUS Address cycle 2 8 2 6 1 1 Logical Addressing 2 8 2 6 1 2 Geographic Addressing 2 8 2 6 1 3 Broadcast Addressing 2 8 2 7 Data Space 2 9 2 7 1 Header Word Format 2 10 2 7 2 Data Word Format 2 10 2 8 Readout 2 11 2 8 1 Single Read from Data Space 2...

Page 5: ...Buffer Memory Pointers 5 1 5 1 3 Buffer Full Empty Conditions 5 2 5 2 Acquisition and Buffering 5 2 5 2 1 Readout of MTDs 5 4 5 2 2 Organization of Data in Events 5 4 5 3 FASTBUS Access to Module 5 4 5 3 1 Control and Status Registers 5 4 5 3 2 Secondary Addressing in Data Space 5 5 5 3 2 1 Default Addressing Mode 5 5 5 3 2 2 Memory Test Mode MTM 5 5 5 4 Mechanisms for FASTBUS Readout 5 6 5 4 1 Lo...

Page 6: ...23 1998 List of Figures 2 2 CSR0 Write Bit Definition 2 4 2 3 CSR1 Bit Definition 2 6 2 4 CSR16 Bit Definition 2 7 2 5 Header word Format 2 10 5 1 Simplified 1881M Interface Buffer Block Diagram 5 1 5 2 1881M Circular Buffer 5 2 ...

Page 7: ......

Page 8: ...on replace any product returned to the Customer Service Department or an authorized service facility within the warranty period provided that the warrantor s examination discloses that the product is defective due to workmanship or materials and has not been caused by misuse neglect accident or abnormal conditions or operations The purchaser is responsible for the transportation and insurance char...

Page 9: ...e it into another program for your use on a single machine Transfer the software and the license to another party if the other party accepts the terms of this agreement and you relinquish all copies whether in printed or machine readable form including all modified or merged versions 1 8 Service Procedure Products requiring maintenance should be returned to the Customer Service Department or autho...

Page 10: ...ers have been properly programmed the module is in acquisition mode and ready to accept a gate pulse The duration of the gate pulse defines the acquisition phase The gate may be provided either via a front panel dECL input via the 1810 CAT module or a nominal 500 ns pulse triggered by a write to CSR0 7 For the duration of this gate signal each of the 64 individual inputs integrate the charge appli...

Page 11: ...ls to avoid excessive pedestal spread and degraded temperature performance The inputs may be configured in several different modes These include 50 Ω single ended 100 Ω differential and 100 Ω pseudo differential It is important to verify the jumper links are correctly configured See Section 3 1 2 for Input options All front panel control inputs to the 1881M are differential ECL compatible with the...

Page 12: ... CSRC0000000h C000003F h 2 5 1 Control and Status Register 0 Functions necessary even for the simplest of operations are contained in CSR0 In order to implement these functions most economically the definition of the bits for CSR0 are not the same for Read and Write operations Some bits are inherently meaningful only for write operations because their status can only be altered by writing to anoth...

Page 13: ...ected through This can be useful during diagnostics of the data acquisition system Priming on LNE CSR0 8 must be enabled when the module is participating in a MDT Multi Block scan Failure to do so will result in the module responding to the transfer with SS 3 the MDT error response LOAD NEXT EVENT Advances Read pointer this is the data space NTA when MTM is set to first location of next event then...

Page 14: ...y test mode allows the direct addressing of the buffer memory using the data space NTA normally writes to data space NTA are ignored When this bit is clear the 1881M acts as a FIFO First In First Out from DSR0 GATE ENABLE This bit must be set to enable the module for data acquisition ENABLE LOGICAL ADDRESS This bit must be set for the module to respond to the logical address as stored in CSR3 This...

Page 15: ...th of time the on board timer permits the user to issue a fast clear to the module after the end of acquisition The fast clear window begins immediately following the end of the gate For the on board FCW to be used the 1810 CAT FCW must be disabled CSR1 2 0 Once the fast clear window has ended the current event is placed in the multiple event buffer and must either be read out or skipped When read...

Page 16: ...during a FASTBUS readout After a Load Next Event command has been issued CSR5 is automatically loaded with the word count for the next event to be read out Only bits 0 through 6 are meaningful Bits 31 7 will read back as 0 CSR5 is set to 00000000 h by a Master Reset 2 5 5 Control and Status Register 7 CSR7 is used to specify the broadcast classes to which an 1881M will respond It is implemented as...

Page 17: ...st operations responded to by the 1881M The case numbers are from the IEEE 960 1989 FASTBUS specification Table 4 3 2 Example address use G 0 and L 1 for broadcasts on the local FASTBUS segment only Case 1 General Broadcast 00000001h All devices respond to subsequent data cycles Case 2 00000005 h Only devices of class N respond to subsequent data cycles Case 3 Sparse Data Scan 00000009 h Devices r...

Page 18: ...2 0 the write buffer is modified by the MTD133 readout circuitry see figure 2 4 When Memory Test Mode is enabled any location within the 8K data space is directly accessible via FASTBUS At any particular time there are 128 one complete buffer secondary addresses DSRs available in data space The buffer currently pointed to by CSR16 can be modified by the Load Next Event command or by writing CSR16 ...

Page 19: ...ut in 32 bit data word The 13 least significant bits are the charge data and the 6 bits from 17 through 22 are the channel identification The most significant byte contains the geographic address parity and the buffer number modulo 4 Here again the parity bit is high or low so as to make the total number of bits in the word even 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 20: ... FASTBUS This may be desired for testing For this purpose the data memory appears as a 8192 x 32 bit word RAM Data may be written into this RAM using random or broadcast modes Block writes to data space are not supported Since the 1881M event manager is not managing this loading the parity checking channel identification and geographic address identification normally present in the data are not pr...

Page 21: ... so that all 1881M ADCs in a crate could be wire OR ed to produce a crate wide CIP This practice is however incompatible with the use of TR7 by the 1810 CAT The 1810 uses TR7 to distribute a reference timing signal to 1879 ADC modules If a 1810 CAT is in the crate the 1881M CSR1 0 must be set to zero 2 12 Example Code The following are examples of some possible general purpose 1881M subroutines Th...

Page 22: ... the next event Note the Data Space NTA must not be directly modified for this feature to work properly Also note that the Secondary Address cycle to Control Space is not required as the 1881M resets the CSRNTA at disconnect void skip_event fb_cycle_pa_csr_multi 0x00000003L General Broadcast fb_cycle_write_word 0x00000400L load next event fb_cycle_disconnect The read_event routine advances the 188...

Page 23: ...ata int word_count int current_channel last_channel I i last_channel 0 Process all the words in the block for i 0 i word_count i Process only data words Header words have channel 127 current_channel channel_number raw_data i if current_channel 63 current_channel 0 update sums summed_data current_channel adc_counts raw_data i The main routine waits for external triggers and processes each event If ...

Page 24: ...nector of the module should mate with the bus connector with modest pressure Note the slot number of the module as it will later be used for addressing 3 1 1 Cables The optimal method of cabling is the use of coax cables as signal cables They generally result in decreased noise pick up and crosstalk This is the preferred method of connection especially for long cable runs However the use of twiste...

Page 25: ... Pin 34 20uF 1 00K J5 Figure 3 1 Input Circuit To operate in a truly balanced configuration pulse transformers should be used on the input In this mode the 1881M should be configured for single ended 50Ω operation In this case however that the AC coupling thus introduced can cause pedestal shift problems at high input rates In order to estimate this effect it is simply necessary to know the amount...

Page 26: ...ed between pins 2 3 left two pins Options J26 J27 Lower right hand corner when inserted CLR input is terminated in 102 Ω To bus CLR remove links from all but the last board on the cable J24 J25 Lower right hand corner When inserted GATE input is terminated in 102 Ωs To bus GATE remove links from all but the last board on the cable J5S J5T J5V J5W along right edge When inserted termination is to gr...

Page 27: ......

Page 28: ...This register must be configured if it is desired to use class N broadcasts After the CSR registers are programmed the unit is ready to acquire data 4 1 3 Acquisition Acquisition begins with the arrival of a gate signal The charge received on all 64 channels during the gate is integrated Charge arriving after the end of the gate is not included Charge integration begins 20 ns nominal after the lea...

Page 29: ... page as the Read pointer a buffer full condition exists This condition is signaled by extending the CIP to prevent additional gates from being accepted It is the users responsibility to ensure that GATEs are not issued when CIP is present on any module This condition continues until an event is read or skipped or master reset Even though there are 64 pages in the buffer because the Read pointer p...

Page 30: ...t manager is not managing this loading however the parity checking channel identification and geographic address identification normally present in the data are not present when read back 4 1 11 Fast Clears A fast clear can be applied any time during the fast clear window This will cause the event just recorded in the front end not to be buffered The write pointer for the buffer will not be increm...

Page 31: ......

Page 32: ...he memory as well as compute the data word parity Events are readout to FASTBUS through a two stage pipeline at up to 10MHz depending on the speed of the Master The FASTBUS readout pipeline stages are required to maintain the maximum transfer rate to the asynchronous FASTBUS The addresses for front end and FASTBUS access are multiplexed at a rate of 40MHz Figure 5 1 Simplified 1881M Interface Buff...

Page 33: ...read pointer The Full and Empty conditions as described apply before a LNE is issued i e if a single event is in the buffer and a LNE is issued the Empty condition would be true even though an event is now ready for readout As events are readout of the MTDs into the circular buffer the WP is incremented to point to the next available buffer Similarly as events are prepared for readout via FASTBUS ...

Page 34: ... edge sensitive common start TDC with a 0 6ns resolution In this application the MTD133 uses a coarse counter with a resolution of 5ns and a CMOS inverter delay line based interpolator to achieve a resolution of 0 625ns The 200MHz clock has very critical duty cycle requirements and is this is corrected using an integration circuit that adjusts the resolution clock to 50 duty cycle An external Op a...

Page 35: ...of the next buffer 5 3 FASTBUS Access to Module 5 3 1 Control and Status Registers Several Control and Status Registers CSR s control the configuration and operation of the 1881M The following is a list of the CSR s contained in the 1881M and a brief description of their function s CSR0 CSR1 primary control and configuration registers These registers contain the configuration bits for all operatio...

Page 36: ...a way similar to a FIFO however no indication will be given when the end last valid data word has been readout The number of words to readout by this method must be ascertained from the header word In the default readout mode re reads of a particular buffer are not directly supported since it is difficult to be certain after the event has initially readout via block transfer what the value of RPA ...

Page 37: ...s value In order to reduce the time required by the module to begin a block transfer LNE can also optionally prime the two stage readout pipeline see figure 5 1 In the module s default data space addressing mode this action is transparent to the user In MTM however the result of this action in to increment the data space NTA twice prior the first data transfer Priming of the readout pipeline does ...

Page 38: ...fer MDT 1 specification Assuming a group on 1881M modules has been configured for a MDT scan as per the specification it must first be established that all modules involved in the scan have data available This could be done for example through a broadcast LNE The scan is initiated by addressing the primary link and beginning a FASTBUS block read The scan proceeds with each module participating in ...

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