LeCroy 1881M, Manual

Page: 13 / 38

Product Description
1881M
July 23, 1998 2-4
Figure 2-2 CSR0 Write Bit Definition
CSR0 After Master Reset or Power-up - 104F0000
h
•
FAST CLEAR: abort conversion and buffering of the last event. The preferred method of clearing the
unit is via a CAT or front panel input as the FAST CLEAR must occur during the FCW which is
difficult to guarantee if carried out over FASTBUS.
•
MASTER RESET: Returns the module to its power-up configuration. All CSR’s are returned to
their power-up states. This is the easiest method of resetting all the output buffers in a crate if the
system goes out of step.
•
CONFIGURE MULTIBLOCK: If either of these bits are set, when accessing the unit all data space
block transfers must be done as part of a multi-block scan. The board in the highest numbered slot
should be programmed as the primary link. The board in the lowest number slot should be
programmed as the end link. The boards in between should be programmed as middle links. The
board set must contiguous. It is acceptable but not recommended (due to increased module to module
token pass time in multi-block block transfers) to have non participating boards in the block
providing they are either multi-block compatible and set to bypass or have their daisy chain lines
connected through. This can be useful during diagnostics of the data acquisition system. Priming on
LNE (CSR0<8>) must be enabled when the module is participating in a MDT (Multi-Block) scan.
Failure to do so will result in the module responding to the transfer with SS=3, the MDT error
response
•
LOAD NEXT EVENT: Advances Read pointer (this is the data space NTA when MTM is set) to
first location of next event, then copies word count from header word of that event to CSR5. This
makes the 1881M ready for a block transfer to readout one entire event.
•
ENABLE PRIMING ON LNE: Enables the first two stages of the internal data pipeline to be primed
when a Load Next Event is issued. This will reduce the token pass time in multi-block scans. This Is
not recommended in MTM mode as it makes the understanding of NTA behavior complicated.
Priming on LNE must be enabled when the module is participating in a MDT (Multi-Block) scan.
Failure to do so will result in the module responding to the transfer with SS=3, the MDT error
response.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR 0 WRITE BIT DEFINITIONS
X
X - USED BITS
* - UNUSED BITS
X X * X * * * X X * * * X * * X X X X X
MASTER RESET - PULSE
FAST CLEAR - PULSE
LOAD NEXT EVENT - PULSE
TRIGGER TEST GATE - PULSE
ENABLE LOGICAL ADDRESS
BYTE 3 BYTE 2 BYTE 1 BYTE 0
X X X
CONFIGURE MULTIBLOCK
00 - BYPASS
01 - PRIMARY LINK
10 - END LINK
11 - MIDDLE LINK
* * X
ENABLE MEMORY TEST MODE
* * * X X
ENABLE GATE
ENABLE PRIMING ON LNE