1881M
Product Description
2-7
July 23, 1998
•
OVERUN DETECT DISABLE: In normal operating modes this bit should NOT be set. When set the
unit will allow the 1881M to overrun. The FULL condition will not prevent further gates and the unit
will cycle from FULL to empty continually. The only purpose of this bit is during setup, when the
readout electronics is not operating and it is desired to setup the trigger with an oscilloscope. When
this bit is reset the front end does not provide a true veto so the experimenter must veto gates with
CIP to prevent half width gates breaking through as CIP finishes.
After Master Reset or Power-up, CSR1 defaults to 00000040
h
(13 bit 50fC mode).
2.5.3
Control and Status Register 3
As per FASTBUS specification, CSR3 is used to store the desired logical address for the unit.
CSR3<31:16> contain the logical address. This register powers up to 0 and is not disturbed by a master
reset, CSR0<30>. CSR3<15:0> are ignored on write and always readback as zero.
2.5.4
Control and Status Register 5
CSR5 is implemented as a 7 bit read/write register used to control the number of words transferred during a
block transfer. It is decremented after each transfer, during a FASTBUS readout. After a Load Next Event
command has been issued, CSR5 is automatically loaded with the word count for the next event to be read
out. Only bits 0 through 6 are meaningful. Bits <31:7> will read back as 0. CSR5 is set to 00000000
h
by a Master Reset.
2.5.5
Control and Status Register 7
CSR7 is used to specify the broadcast classes to which an 1881M will respond. It is implemented as a 4
bit read/write register. Bits 3 through 0 correspond to broadcast classes 3 through 0 respectively. If bit N
is set, the 1881M will be selected by a broadcast to class N devices. CSR7 is not affected by Master
Reset. The unit will always ignore broadcasts to groups 4-7.
2.5.6
Control and Status Register 16
CSR16 is implemented as a 16 bit read-write register used to indicate and control the location of the read
and the write buffer addresses. CSR16 <13:8> indicate the next buffer to be readout, and CSR16 <5:0>
indicate the next buffer address to be filled. Master Reset and Power-up reset CSR16 to 00003F00
h
.
Unused bits always read back as zero.
Figure 2-4 CSR16 Bit Definition
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSR 16 BIT DEFINITIONS
X - USED BITS
* - UNUSED BITS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
0
0
0
0
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
0
0
X
X
0
0
X
X
READ BUFFER
WRITE BUFFER
X
X
CSR16 POWER-UP OR MASTER RESET STATE: 0x00003F00
Summary of Contents for 1881M
Page 1: ...MODEL 1881M 64 CHANNEL FASTBUS ADC ...
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