Lavry DA2002 Operation Manual Download Page 12

DA2002 

 

Theory of Operation

 

10 
 

 
The calibration process takes a long time because the node adjustment is interactive (adjusting a 
node causes some miss-adjustment at all the other nodes). A single calibration cycle consists of 
reading and adjusting of all the nodes. The processor repeats the calibration cycle numerous 
times until all the nodes are set properly. Though nodes interaction exists during the adjustment 
process, the overall network is guaranteed to converge on a solution by design. Calibrating a 
DA2002 for the first time (at the factory) often exceeds 25 minutes. Once calibrated, the settings 
are stored in non volatile ram for future startup point of reference, thus all future adjustments are 
initialized to the last settings. Therefore the initial tolerance of the components is pre calibrated 
already, and each new calibration needs to deal only with component drift under the same given 
temperature conditions (ovenized components). The remaining calibration at each subsequent 
power on takes less then 2 minutes typically. 
      

Timing and Deglitcher 

The conversion from a digital sample value to an analog voltage consists of translating a digital 
code to a corresponding setting of analog switches and multiplexers to tap the appropriate 
voltage from the analog nodes. Such switching causes unwanted glitch energy to come into play. 
The glitch energy is code and signal dependent and can not be removed by filtering. The purpose 
of the deglitcher circuit (see diagram) is to block the signal from feeding to the output for long 
enough time after each transition, thus allowing the glitches enough time to disappear, and for 
each new analog sample to accurately settle to its final value. 
 
The deglitcher circuit is in off state about half a sample time, and on for the rest of the time. The 
on time is the critical time and no digital activity takes place anywhere near the analog circuits. 
The settled signals are fed to the output filter with minimum disturbance.  The deglitcher off time 
settling requires the circuit to block as much of the transitions from feeding forwards to the 
output filter.  
 
The blocking requirement is very demanding because a transition of many volts between two 
adjacent sample values should feed forward less than a microvolt. A single switch can not yield 
such blocking performance. The deglitcher utilizes four switches: the first switch shunt (shorts) 
the signal to ground. The remaining signal is connected to the second switch that is in open state. 
Whatever comes through is shunted to ground by the third switch. The remaining tiny energy is 
further blocked by the fourth opened series switch.    
 
During the deglitcher on state, the shunt switches (switch one and three) are opened and the 
series switches (switch two and four) are shorted to allow the signal path to the output. The 
deglitched circuit utilizes DMOS technology thus providing extremely low resistance during the 
“on” state. The remaining problems due to “on” state resistance variations are neutralized by use 
of the strong feedback of the deglitcher amplifier.     
 
The main reason for using DMOS transistors is their sub nanosecond switching capabilities. The 
jitter critical timing point is all at the deglitcher circuit. Each sample value must exist over the 
same time period thus precise deglitcher turn on and turn off are critical for good results. In fact 
switching during deglitcher blocking time can be somewhat sloppy, as long as the signals are 
well settled prior to turn on. Fighting the jitter wars means feeding the deglitcher circuit a precise 
jitter free on / off drive signal. 
 

Summary of Contents for DA2002

Page 1: ...Model DA2002 High Resolution Digital to Analog Converter Operations Manual ...

Page 2: ...Lavry Engineering Inc P O Box 4602 Rolling Bay WA 98601 360 598 9757 http www lavryengineering com E Mail techsupport lavryengineering com Revision 1 7C December 7 2011 ...

Page 3: ...ormance and pure enjoyment of the artistic experience The no compromise approach of designer Dan Lavry to the architecture of the DA2002 resulted in a unique design with unparalleled accuracy As a classically trained musician he brings more than decades of engineering experience to his designs a lifetime of playing and listening to acoustic performance has honed his ability to discriminate subtle ...

Page 4: ...omatic self calibration A large number of extra codes enable the addition of digital DC offset to the signal path without signal clipping The DC offset provides superior low level detail by keeping low level signals away from the most significant bit transitions A quad switch deglitcher circuit removes the unwanted transition glitch energy In both PLL Mode and CrystalLock Mode the DA2002 eliminate...

Page 5: ...nal Connection 5 Analog Outputs 6 Analog Output Level 6 Turn On Sequence 7 Polarity Inversion 7 PLL Mode and CrystalLock Mode 8 Power and Fusing 8 Maintenance 8 Part II Theory of Operation Oven control 9 Calibration 9 Timing and Deglitcher 10 Jitter Removal 11 Output Filter and Drivers 11 Part III Specifications 12 Limited Warranty 13 ...

Page 6: ...DA2002 Table of Contents 4 ...

Page 7: ...CT between Search Mode and Manual Mode The mode selected is retained when power is removed In Search Mode each time the INPUT SELECT button is pressed the DA2002 will scan the inputs for the next input with a valid signal present It will skip the inactive input connectors where no signal is present The default setting is Search Mode enabled In Manual Mode each press of the INPUT SELECT button move...

Page 8: ...d mode position the jumpers are set to 90 degrees with respect to the front panel Pin 1 of the XLR connectors is connected to ground potential for proper cable shield connection The LEFT OUTPUT and RIGHT OUTPUT IEC signals are always unbalanced and are not affected by J8 and J10 jumper settings Analog Output Levels The analog output level at the IEC connectors for a full scale digital input signal...

Page 9: ...tive the unit steps through the input ports continuously as indicated by the input select lamps if in Search Mode Most DAC s contains relays for the purpose of muting the output during turn on allowing the DAC to settle to proper operating conditions The DA2002 contains no relays in order to avoid signal degradation associated with relay contacts The unit minimizes turn on spikes by incorporating ...

Page 10: ...e through a small window in the hinged cover located next to the AC power switch and input connector To change or check the fuses or change the operating voltage carefully open the cover by lifting the right edge and pull the red fuse holder straight out of the power input module The voltage is set by turning the red fuse holder so the desired operating voltage is visible when the fuse holder s co...

Page 11: ...mparison against a reference level tells the processor the required adjustments The voltage difference between any given network node and the reference is greatly amplified and then fed to a strobing comparator see multiplexers for calibration and error amplifier and comparator gain blocks in the simplified diagram The processor strobes the comparator and reads its output The strobing is repeated ...

Page 12: ...l value The deglitcher circuit is in off state about half a sample time and on for the rest of the time The on time is the critical time and no digital activity takes place anywhere near the analog circuits The settled signals are fed to the output filter with minimum disturbance The deglitcher off time settling requires the circuit to block as much of the transitions from feeding forwards to the ...

Page 13: ...hanged by tiny amounts 1ppm and not very often 15 seconds or more in a manner allowing it to track only very long term average drift Using such an approach with ordinary PLL will cause loss of lock because the slight variations in incoming data rate cause loss of correspondence between the input and the too steady of a clock circuit The DA2002 CrystalLock approach stores enough data in a dedicated...

Page 14: ...k mode varispeed Crystal lock tracking 1ppm 15 seconds Channel separation 100dBFs at 1KHz Flatness response 05dB 10Hz 20KHz Phase linearity 2 degrees 10Hz 20KHz Digital inputs Two AES EBU 110 Ohm transformer isolated One Consumer 75 Ohm transformer isolated Analog outputs AES EBU balanced 4 2V R M S into 600 ohms AES EBU balanced 4 5V R M S into 100Kohms AES EBU unbalanced 2V R M S into 600 ohms A...

Page 15: ...diction LIMITS AND EXCLUSIONS LAVRY ENGINEERING DOES NOT BY VIRTUE OF THIS AGREEMENT OR BY ANY COURSE OF PERFORMANCE COURSE OF DEALING OR USAGE OF TRADE MAKE ANY OTHER WARRANTIES EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION ANY WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE OR NONINFRINGEMENT AND ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED LAVRY ENGINEERING EXPRESSLY...

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