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Lattice ORCA ORSO42G5, Technical Note

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Lattice ORCA ORSO42G5 Technical Note Download Page 4

 

Evaluating the ORCA ORSO42G5 with the

Lattice Semiconductor

High-Speed SERDES Board

 

4

 

Transmit Eye Diagram Setup Requirements 

 

You will need the following to complete this evaluation:

• ORSO42G5 High-Speed SERDES Board configured as described earlier.
• Orso4_felb6.bit bitstream and bitstream programming devices (ispDOWNLOAD cable and ispVM running 

on a PC).

• ORCAstra GUI application and tx_eye.fpm macro.
• Scope to view data eye and high speed SMA cables (50

 

Ω

 

 up to 3.0Gb/s) with bias tees at the input to the 

scope.

• Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock 

source to the Lattice High-Speed SERDES Board and to the trigger input of the scope. (Note: The eye mea-
surements could alternately be made using a Serial Data Analyzer. In that case no trigger connection is 
required.)

• 5V DC wall power supply.
• 1.5V DC supply for the bias tees

A typical setup is shown in Figure 4.

 

Figure 4. Transmit Eye Diagram Setup

 

Transmit Eye Diagram Test Procedures (SONET Scrambled Data Eye) 

 

1. Connect the system as shown in Figure 4. The scope SMA cables should be connected to the 

HDOUTP_Bx and HDOUTN_Bx SMA connectors on the board. 

2. Power-up the system

3. Start the clock generator and provide a nominal 155.52MHz CML reference clock.

4. Download the orso4_felb6.bit bitstream into the ORSO42G5. 

5. Run the tx_eye.fpm macro using the pull-down menu in the ORCAstra application. This macro will set up 

the AC and AD channels in a SONET AUTO_TOH transmit mode using the SONET scrambler.

6. Observe the SONET scrambled data eye on the scope.

+

-

5V DC 4A

Power Supply

1.5V DC 0.5A

Power Supply

Note: Do not use
stand-alone bias tees
on channels (AA and BA).
Those channels have a
built-in bias tee.

ORSO42G5

DUT

REFCLKN_B

REFCLKP_B

HDOUTP_Bx

Picosecond

5575A

Bias Tee

Picosecond

5575A

Bias Tee

Agilent 86100B DCA

(or equivalent)

HDOUTN_Bx

ispDOWNLOAD

Cable

ORCAstra

Interface Cable

High = 500mV

Low = 0V

155MHz

Trigger In

High-Speed SERDES Board

Agilent 81130A

Clock Source

(or equivalent)

Computer

Agilent 816112

20GHz

Electrical

Module

(or equivalent)

Summary of Contents for ORCA ORSO42G5

Page 1: ...umes the baseline board configuration listed below The user is also encouraged to experiment with other configurations All jumpers should be in their default position and default programming in the ispPAC POWR1208 as described in the Evaluation Board User Manual This will apply power in the recommended sequence and provide 3 3V VDDIO to all banks ispDOWNLOAD cable pDS4102 DL2 connected to the para...

Page 2: ...p back ORSO4_FELB6 Bitstream The orso4_felb6 bit design has been created as a base for all the described evaluation setups for the ORSO42G5 device As shown in Figure 3 the design takes advantage of the four SERDES channels available on the board The orso4_felb6 bitstream and the ORCAstra macros used in the tests are included in the package downloaded from www latticesemi com products devtools hard...

Page 3: ...servation and measurement of the data eye generated by the device The ORSO42G5 device s major mode will produce a SONET scrambled data eye The same experimental setup can be used for near end loop back tests Other data pattern eye diagrams can be measured using far end loop back setups discussed later in this docu ment In this example either channel AC or AD can be used to evaluate a SONET scrambl...

Page 4: ...ansmit Eye Diagram Setup Transmit Eye Diagram Test Procedures SONET Scrambled Data Eye 1 Connect the system as shown in Figure 4 The scope SMA cables should be connected to the HDOUTP_Bx and HDOUTN_Bx SMA connectors on the board 2 Power up the system 3 Start the clock generator and provide a nominal 155 52MHz CML reference clock 4 Download the orso4_felb6 bit bitstream into the ORSO42G5 5 Run the ...

Page 5: ... 3 Far end Loop back For a Far End Loop back FELB test using the ORSO42G5 device the reference clock for the ORSO42G5 and for the data source must be frequency locked This is a mandatory requirement since the ORSO42G5 transmitter always uses the local reference clock Three types of FELB can be performed with the ORSO42G5 device Each type uses a different data path for the transmit and receive bloc...

Page 6: ...tion 0xF6F6F6F628282828 SONET framing is established and the data is optionally descrambled After framing is established the aligned 32 bit data is transmitted to the FPGA along with a frame pulse DOUTBx_FP to indicate the start of the SONET frame The orso4_felb6 bit design uses an asynchronous FIFO to cross clock domains to the local reference clock REFCLK The data is then sent back into the embe...

Page 7: ...he data back to the transmit interface to the embedded ASIC core as 32 bit data and frame pulse DINBx_FP for each channel Inside the Tx SONET block TOH bytes are optionally inserted and the 32 bit data is optionally re scrambled The data is then sent through the MUX block converted back to 8 bits serialized and transmitted via the CML buffer Setup Requirements Far End Loop back Testing You will ne...

Page 8: ...ing the ORCAstra application SONET FELB 1 Connect the system as shown in Figure 8 The data SMA cables should be connected to the HDIN_Bx and HDOUTN_Bx SMA connectors on the board 2 Power up the system 3 Start the clock generator to provide a nominal 155 52MHz CML reference clock 4 Download the orso4_felb6 bit bitstream into the ORSO42G5 5 Run the sonet_felb fpm macro using the pull down menu in th...

Page 9: ...lication can be used to control this selection When AUTO_TOH mode is enabled the Tx SONET block inserts all of the TOH bytes in the SONET frame This mode overwrites any default TOH values If AUTO_TOH mode is used the SONET scrambler descrambler must also be used An AUTO_SOH mode can also be selected using the ORCAstra application In this mode A1 A2 and or B1 bits are optionally inserted by the cor...

Page 10: ...minated to ground they do not provide the required termination bias voltage When this equip ment is directly connected to the SERDES output it will provide an incorrect DC bias and prevents proper output buffer operation Inserting the bias tee module in the SERDES output connection to the oscilloscope allows the application of the required dc bias condition and provides the dc voltage translation ...

Page 11: ...cy ranges and DC cur rent levels from several different vendors Lattice uses a Picosecond Pulse Lab bias tee More detailed character ization and application documents are available from this vendor See the References section at the end of this document Q Can the SERDES output be observed without a bias tee module Yes in two different ways as shown below 1 For AC coupled SERDES interface applicatio...

Page 12: ...on voltage should be set to the VDDOB supply voltage used on the High Speed SERDES Board 1 5V if internal supply is being used This is the best means of observing the Tx data out put signals for DC coupled applications since it eliminates any possible signal degradation caused by bias tee and DC blocking elements References Bias Tee Model 5575A Picosecond Pulse Labs Boulder CO www picosecond com 5...

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