Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor
High-Speed SERDES Board
2
Figure 1. Near-end Loop-back
Far-end Loop-back (FELB) is defined as the data path from the SERDES input, to parallel data and back out the
SERDES as shown in Figure 2. Three different internal FELB path options are discussed: SERDES-only, SONET
and Aligned SONET.
Figure 2. Far-end Loop-back
ORSO4_FELB6 Bitstream
The orso4_felb6.bit design has been created as a base for all the described evaluation setups for the ORSO42G5
device. As shown in Figure 3, the design takes advantage of the four SERDES channels available on the board.
The orso4_felb6 bitstream and the ORCAstra macros used in the tests are included in the package downloaded
from www.latticesemi.com/products/devtools/hardware/orso42g5-board/index.cfm.
FPGA
SERDES
Serial Data
32-bit Data
Reference Clock
ORSO42G5
FPGA
Data Source
SERDES
Serial Data
32-bit Data
Reference Clock
ORSO42G5
