Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor
High-Speed SERDES Board
3
Figure 3. orso4_fleb6 Design
An STS48 frame generator in the FPGA logic can supply the transmit data source for all tests. Channels AC and
AD can be used in a Transmit-only mode to observe the transmit eye diagram, or can be used for loop-back testing.
Channels AC and AD use the FIFO in the Embedded Core for clock domain crossing and can only be used in
SONET mode. Dual channel alignment can be performed on these two channels.
In channels BC and BD, the clock domain crosses the FIFO in the FPGA logic. These channels can be used in the
SERDES-only mode or the SONET mode.
Transmit Eye Diagram
One of the most fundamental evaluations that can be performed with the Lattice High-Speed SERDES Board is
observation and measurement of the data eye generated by the device. The ORSO42G5 device’s major mode will
produce a SONET scrambled data eye. The same experimental setup can be used for near-end loop-back tests.
Other data pattern eye diagrams can be measured using far-end loop-back setups discussed later in this docu-
ment.
In this example, either channel AC or AD can be used to evaluate a SONET scrambled data eye. Both channels
use the SONET Transmit processing block, which includes a SONET scrambler. This scrambled data eye can then
be observed on the AC or AD HDOUT CML pins.
RWCKBx
TSYSCLKBx
TCK78B
ORSO42G5
HDIN_Ax
HDOUT_Ax
HDIN_Bx
HDOUT_Bx
Tx SERDES
Tx SERDES
Rx SERDES
Rx SERDES
RWCKAx
TSYSCLKAx
TCK78A
AC/AD
BC/BD
Data
Generator/
Analyzer
Tx SONET
Tx SONET
Rx SONET
Rx SONET
32-bit data,
DOUTBx_FP
32-bit data,
DOUTAx_FP
STS48
FP Gen
FIFO
FIFO
REFCLK_A
REFCLK_B
FPGA ASIC
ORCAstra
sysBUS
USI
DOUTBC_OOF
DOUTBD_OOF
RCK78B
DOUTAC_OOF
DOUTAC_FP
DOUTAC_B1_ERR
DOUTAC_SPE
TCK78B
DOUTAD_OOF
