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LatticeMico

8

 Microcontroller

Lattice Semiconductor

User’s Guide

Register File

 

The register file is implemented using dual ported distributed RAM. It contains 32 8-bit entries. Two values can be
simultaneously read from the register file.

 

Scratch Pad RAM (Internal)

 

The internal scratch pad memory has 32 entries. It can be addressed directly or indirectly (via a register). Indirect
addressing mode is not available if external scratch pad memory is attached.

 

Optional External Scratch Pad

 

The external scratch pad provides an additional 256 bytes of memory. It can be implemented using either distrib-
uted RAM or using an EBR. The external scratch pad memory can be addressed via indirect addressing only.

 

Hardware (Circular) Call Stack

 

When a 

 

call

 

 instruction is executed, the address of the next instruction is pushed into the call stack, a 

 

ret

 

(return) instruction will pop the stack and continue execution from the location at the top of the stack. 

An interrupt also causes the address of the instruction that would have executed next to be pushed into the call
stack. The 

 

reti

 

 (return from interrupt) instruction will pop the stack and continue from the location at the top of the

stack.

The stack is implemented as a circular buffer and any program execution will continue from an undefined location in
case of a stack overflow or underflow.

 

Interrupt Handling

 

The microcontroller has one interrupt source, which is level sensitive. The interrupt can be enabled or disabled by
software (

 

cli

 

 = clear interrupt, 

 

sti

 

 = set interrupt). When an interrupt is received, the address of the next instruc-

tion is pushed into the call stack and the microcontroller continues execution from the interrupt vector (address 0).
The flags (carry and zero) are copied to shadow locations. The 

 

interrupt ack 

 

line is set high and the acknowl-

edge line is held high for the entire duration of interrupt handling. Once the interrupt has been acknowledged the
interrupt line should be set to 0.

 

reti

 

 instruction will pop the call stack and transfer control to the address on top of the stack. The Flags (carry

and zero) are restored from the shadow locations. The interrupt acknowledge line is set to low.

The microcontroller cannot handle nested interrupts.

 

Input/Output

 

Input and output are done via “ports”. Up to 256 port numbers are allowed. The lower 32 ports can be addressed
directly (using the 

 

import

 

 and 

 

export

 

 instructions), or indirectly (using the 

 

importi

 

 and 

 

exporti

 

 instructions).

The upper 224 ports can be accessed by indirect addressing only (by the 

 

importi

 

 and 

 

exporti

 

 instructions).

The port number (0-31 of 

 

import

 

 

export

 

 and 0-255 for 

 

importi

 

 and 

 

exporti

 

 instructions) is presented at the

external interface for two cycles.

For 

 

import

 

 and 

 

importi

 

 instructions, the 

 

ext_io_rd

 

 signal is strobed in the same cycle as the input values are

sampled. The address signal is 

 

ext_addr

 

 and the input signals are 

 

ext_io_din

 

. Both the address and the I/O

read strobe are driven in the second cycle. In the case of the 

 

importi

 

 instruction, the 

 

ext_addr

 

 signal is driven

from the register file; otherwise, for the 

 

import

 

 instruction, it is driven directly from the instruction. Figure 2 shows

the waveform corresponding to a read.

Summary of Contents for LatticeMico8

Page 1: ...ter medical industrial and automotive The core consumes minimal device resources less than 200 Look Up Tables LUTs in the smallest configuration while maintaining a broad feature set Features 8 bit Da...

Page 2: ...ar interrupt sti set interrupt When an interrupt is received the address of the next instruc tion is pushed into the call stack and the microcontroller continues execution from the interrupt vector ad...

Page 3: ...ite In the case of the exporti instruction the ext_addr signal is driven from the register file otherwise for the export instruction it is driven directly from the instruction Figure 3 Microcontroller...

Page 4: ...ith the carry out from the addition The zero flag is set to 1 if all the bits of the result are 0 ADDIC Rd CC Rd Rd CCCCCCCC Carry Flag add register constant and carry flag The carry flag is updated w...

Page 5: ...o 1 if all the bits of the result are 0 SUBIC Rd C Rd Rd CCCCCCCC Carry Flag subtract constant with carry from register The carry flag is set to 1 if the result is negative The zero flag is set to 1 i...

Page 6: ...CCC bitwise AND register with constant The zero flag is set to 1 if all the bits of the result are 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0 CY Flag U...

Page 7: ...CC bitwise XOR register with constant The zero flag is set to 1 if all the bits of the result are 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0 CY Flag U...

Page 8: ...eration is not written back The zero flag is set to 1 if all the bits of the result are 0 TESTI Rd CC Perform a bitwise AND between Rd and Constant update the zero flag The result of the AND operation...

Page 9: ...to the carry flag The zero flag is set to 1 if all the bits of the result are 0 ROL Rd Rb Rotate left Register B is shifted left by one bit The highest order bit is shifted into the lowest order bit T...

Page 10: ...y Flag 1 Set carry flag CLRZ Zero Flag 0 Clear zero flag 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 1 1 CY Flag Updated Zero Flag Updated Yes Yes 17 16 15 14...

Page 11: ...bel from the current PC If zero flag is 0 then execution continues with the following instruction The offset can be 512 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1...

Page 12: ...f Label Else PC PC 1 Branch if not carry If carry flag is not set the PC is incremented by the signed offset of the label from the current PC If carry flag is set then execution continues with the fol...

Page 13: ...by the signed offset of the label from the current PC If the zero flag is set then execu tion continues from the following instruction CALLC Label If Carry Flag 1 then Push PC 1 into Call Stack PC PC...

Page 14: ...is pushed into the call stack and the PC is incremented by the signed offset of the label from the current PC RET PC Top of Call Stack Pop Call Stack Unconditional return PC is set to the value on th...

Page 15: ...RT Rd Port Port Value Port Rd Output value of Register D to Port Port can be 0 31 EXPORTI Rd Rb Port Value Rb Rd Output value of Register D to Port designated by Register B Port can be 0 255 17 16 15...

Page 16: ...nated by constant SS The location address can be 0 31 SSPI Rd Rb Scratch Pad Rb Rd Store into scratch pad memory indirect Store value of register D into scratch pad memory location designated by regis...

Page 17: ...external scratch pad memory The ext_dout is used to write data into the external memory The address bus ext_addr is also shared Assembler and Instruction Set Simulator The software tools for the Latti...

Page 18: ...in the Instruction Set section Pseudo Ops The Assembler supports the following pseudo ops Option Comment nop Expanded by the Assembler to mov R0 R0 An instruction without side effects Labels Label de...

Page 19: ...er will terminate with an error if the org directive is given a location which is less than the current local counter value equ This directive can be used to assign symbolic names to constants The syn...

Page 20: ...ails ix Program file is in hexadecimal format default This is the file generated by the Assembler with the vx options default ib Program file is in binary format This is the file generated by the Asse...

Page 21: ...following commands should be used in the Unix and Windows environments Unix and Cygwin Environments gcc o isp8sim isp8sim c Windows Environment cl o isp8sim_win isp8sim c Example To display the featu...

Page 22: ...e of program mov r7 r5 mov r5 r6 andi r5 0x0f masking r5 to get the speed mov r25 r5 cmpi r7 0x10 bz phase2 cmpi r7 0x20 bz phase2 b start phase2 cmpi r25 0x01 bz phase3 cmpi r25 0x02 bz phase3 cmpi r...

Page 23: ...4 LCMX01200C 4 214 71 109 78 6 LCMXO1200C 4 LFE2 50E 5 220 71 132 90 7 LFE2 50E 5 2 32 Regs 16 Int SP No Ext SP LFXP3C 4 LFEC3E 4 247 71 138 62 4 LFXP3C 4 68 8 LFEC3E 4 LCMXO1200C 4 248 71 125 71 9 L...

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