Lattice Semiconductor MachXO5-NX Development Kit, User Manual

Page: 30 / 64

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30 FPGA-EB-02052-0.90
AK_SCL/AK_SDA with SCL1/SDA1 and SCL2/SDA2, or add bridge resistors according to Table 8.14 to connect all of them
to SCL0/SDA0 for bridge interconnections on board without involvement of FPGA. You also need to setup the design
with tri-state mode for outputting high with pull up resistors. If there is no pull up setup on the counterpart boards or
internal GPIOs of FPGA, you can add JP12 and JP13 to leverage the R33 and R34 for pulling up bridge SCL0/SDA0 to
selectable VCCIO2. Take care that the DPHY0_SCL/DPHY0_SDA are special case. They need dedicate pull up resistors
R233/R234 due to they are supported from 1.8 V I/O Bank 9. Also, R233/R234 can be used to pull up SCL0/SDA0 by
adding R229/R228 when Bank 7 is selected to support 1.8 V for FX12 header I
2
C control. At this time, JP12 and JP13
should be removed and R224/R225 or R226/R227 should be added to leverage the 1.8 V pull up for I/O Bank 7.
Table 8.14. I
2
C Connections
Extend header MachXO5-25 Bank
MachXO5-25 Ball
Location for JTAG
Net Name
Bridge Resistor to
SCL0/SDA0
Versa Header
(J9)
0 D5 EXPCON_IO13 R35 (DNI)
B5 EXPCON_IO15 R37 (DNI)
Aardvark Header
(J7)
3 M19 AK_SCL R231 (DNI)
M20 AK_SDA R230 (DNI)
Arduino Header
(J2)
3 N19 AR_SCL R45 (DNI)
N18 AR_SDA R44 (DNI)
FX12 Headers
(U4/U5)
7 R5 SCL1 R224 (DNI)
R4 SDA1 R225 (DNI)
FX12 Headers
(U4/U5)
7 R7 SCL2 R226 (DNI)
R6 SDA2 R227 (DNI)
Raspberry Pi Header (J6) 8 K1 RASP_ID_SC R85 (DNI)
K2 RASP_ID_SD R87 (DNI)
Raspberry Pi Header (J6) 8 L7 RASP_IO03 R96 (DNI)
L8 RASP_IO02 R84 (DNI)
Camera Header
(J27)
9 H6 DPHY0_SCL R229 (DNI)
H5 DPHY0_SDA R228 (DNI)
8.9. ADC and Potentiometer
There are two dedicate ADC input pairs for MachXO5-25. This board provides multiple application options. For default population,
one pair of ADC0 is used to measure the core VCC voltage drop through a 10 mΩ resistor R112. Therefore, the core VCC current is
calculable, as shown in
Figure 8.3 . Positive input of another pair ADC1 is connected to a 10 kΩ Trimmer Potentiometers (POT1)
which provides voltage variation from 0 V to selectable VCCIO4, as shown in Figure 8.4 . The negative input of ADC1 is grounded
through 1 kΩ resistor.
Figure 8.3. Circuit Design for ADC0