Lattice Semiconductor MachXO5-NX Development Kit, User Manual

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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FPGA-EB-02052-0.90 31
Figure 8.4. Circuit Design for ADC1
Rotate the Trimmer clockwise to decrease the voltage, as shown in Figure 8.5 . To increase the voltage to ADCP1, rotate
the POT counter-clockwise.
Decreasing
Wiper
Voltage
Wiper
CW
CCW
Clockwise
1
2
3
Figure 8.5. Trimmer Wiper Description
Optionally, both ADC pairs are also routed to PMOD like header J28. For their signal assignment, refer to Table 8.15.
Table 8.15. J28 (DNI) Header Pin Connections
J28 Pin Number Net Name MachXO5-25 Ball Location Application Notes
1 MDIR0 W1 Within IO Bank 7
2 MEN0 V5 Within IO Bank 7
3 ADCP0 Y16 Remove R168 for separation
4 ADCN0 Y17 Remove R169 for separation
5 GND — —
6 VCCIO7 — 1.8V/3.3V selectable
7 MDIR1 W2 Within IO Bank 7
8 MEN1 V6 Within IO Bank 7
9 ADCP1 Y18 Remove R82 for separation
10 ADCN1 Y19 Remove R80 for separation
11 GND — —
12 VCCIO7 — 1.8V/3.3V selectable