25
LatticeSC PCI Express x4 Evaluation Board
Lattice Semiconductor
User’s Guide
Figure 16. Parallel Flash
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
F
LASH
_A9
F
LASH
_A8
F
LASH
_A7
F
LASH
_A6
F
LASH
_A5
F
LASH
_A4
FL
A
S
H_
WE
_
N
FL
A
S
H_
WP
_
N
FL
A
S
H_
O
E
_
N
T
M
S_XO
TDI_
X
O
TDO
_
X
O
F
LASH
_A3
F
LASH
_A2
F
LASH
_A1
F
LASH
_A0
FL
A
S
H_
D0
FL
A
S
H_
D1
FL
A
S
H_
D2
FL
A
S
H_
D0
FL
A
S
H_
D3
FL
A
S
H_
D4
FL
A
S
H_
D5
FL
A
S
H_
D6
FL
A
S
H_
D7
FL
A
S
H_
D8
FL
A
S
H_
D9
FL
A
S
H_
D1
0
FL
A
S
H_
D1
1
FL
A
S
H_
D1
2
FL
A
S
H_
D1
3
FL
A
S
H_
D1
4
FL
A
S
H_
D1
5
FL
A
S
H_
D1
FL
A
S
H_
D2
FL
A
S
H_
D3
FL
A
S
H_
CL
K
GSR
N
FL
A
S
H_
D4
FL
A
S
H_
D5
FL
A
S
H_
D6
FL
A
S
H_
D7
FL
A
S
H_
D8
FL
A
S
H_
D9
FL
A
S
H_
D1
0
FL
A
S
H_
D1
1
FL
A
S
H_
D1
2
FL
A
S
H_
D1
3
FL
A
S
H_
D1
4
FL
A
S
H_
D1
5
DO
NE
TCK
F
LASH
_D
[0.
.31]
FL
A
S
H_
WE
_
N
FL
A
S
H_
WP
_
N
FL
A
S
H_
RE
S
E
T_
N
FL
A
S
H_
O
E
_
N
INITN
FL
A
S
H_
CE
_
N
F
LASH
_A9
F
LASH
_A8
F
LASH
_A7
F
LASH
_A6
F
LASH
_A5
F
LASH
_A4
F
LASH
_A3
F
LASH
_A2
F
LASH
_A1
F
LASH
_A0
F
LASH
_A19
F
LASH
_A18
F
LASH
_A17
F
LASH
_A16
F
LASH
_A15
F
LASH
_A14
F
LASH
_A13
F
LASH
_A12
F
LASH
_A11
F
LASH
_A10
F
LASH
_A19
F
LASH
_A[
0.
.19]
FL
A
S
H_
CE
_
N
FL
A
S
H_
RD/B
Y
F
LASH
_AD
V_N
DA
TA
2
DA
TA
3
DA
TA
4
DA
TA
5
DA
TA
6
DA
TA
7
DA
TA
0
DA
TA
1
FL
A
S
H_
RD/B
Y
F
LASH
_A18
F
LASH
_A17
F
LASH
_A16
F
LASH
_A15
F
LASH
_A14
F
LASH
_A13
F
LASH
_A12
F
LASH
_A11
F
LASH
_A10
F
LASH
_AD
V_N
LOAD
ER
_C
K
FL
A
S
H_
D1
6
FL
A
S
H_
D1
7
FL
A
S
H_
D1
8
FL
A
S
H_
D1
9
FL
A
S
H_
D2
0
FL
A
S
H_
D2
1
FL
A
S
H_
D2
2
FL
A
S
H_
D2
3
FL
A
S
H_
D2
4
FL
A
S
H_
D2
5
FL
A
S
H_
D2
6
FL
A
S
H_
D2
7
FL
A
S
H_
D2
8
FL
A
S
H_
D2
9
FL
A
S
H_
D3
0
FL
A
S
H_
D3
1
FL
A
S
H_
D1
6
FL
A
S
H_
D1
7
FL
A
S
H_
D1
8
FL
A
S
H_
D1
9
FL
A
S
H_
D2
0
FL
A
S
H_
D2
1
FL
A
S
H_
D2
2
FL
A
S
H_
D2
3
FL
A
S
H_
D2
4
FL
A
S
H_
D2
5
FL
A
S
H_
D2
6
FL
A
S
H_
D2
7
FL
A
S
H_
D2
8
FL
A
S
H_
D2
9
FL
A
S
H_
D3
0
FL
A
S
H_
D3
1
FL
A
S
H_
RE
S
E
T_
N
FL
A
S
H_
IND/WA
ITN
FL
A
S
H_
IND/WA
ITN
FL
A
S
H_
CL
K
_
INP
U
T
F
LASH
_C
LK_I
N
PU
T
PR
OGR
AM
N
3_3V
2_5V
2_5V
3_3V
3_3V
2_5V
12_0V
2_5V
T
M
S_XO
[2
]
TDI_
X
O
[2
]
TDO
_
X
O
[2
]
GSR
N
[2
]
DO
NE
[2
]
TCK
[2
]
FL
A
S
H_
CL
K
[9
]
INITN
[2
]
DA
TA
[0
..7
]
[2
]
LOAD
ER
_C
K
[2
]
PR
OGR
AM
N
[2
]
Ti
tl
e
Siz
e
Projec
t
R
ev
D
at
e:
Sheet
of
SC8
0
X4
PCI
EXPRESS Ca
rd
3.
0
Par
a
llel F
lash
C
11
11
Ti
tl
e
Siz
e
Projec
t
R
ev
D
at
e:
Sheet
of
SC8
0
X4
PCI
EXPRESS Ca
rd
3.
0
Par
a
llel F
lash
C
11
11
Ti
tl
e
Siz
e
Projec
t
R
ev
D
at
e:
Sheet
of
SC8
0
X4
PCI
EXPRESS Ca
rd
3.
0
Par
a
llel F
lash
C
11
11
CPLD RESET
C5
0
7
100N
F
-0603SM
T
C5
0
7
100N
F
-0603SM
T
C
513
100N
F
-0603SM
T
C
513
100N
F
-0603SM
T
R
217
2_2K-0603SM
T
R
217
2_2K-0603SM
T
R2
2
0
1K-0603SM
T
R2
2
0
1K-0603SM
T
C
512
10N
F
-0603SM
T
C
512
10N
F
-0603SM
T
J1
1
2
J
U
M
PER
1
J1
1
2
J
U
M
PER
1
1
2
C
508
10N
F
-0603SM
T
C
508
10N
F
-0603SM
T
C5
0
9
100N
F
-0603SM
T
C5
0
9
100N
F
-0603SM
T
R
219
1K-0603SM
T
R
219
1K-0603SM
T
J1
1
4
H
EAD
ER
3X1
J1
1
4
H
EAD
ER
3X1
1
1
2
2
3
3
U2
3
29C
D
032G
U2
3
29C
D
032G
A1
5
A1
A1
4
A2
VCC
A3
AC
C
A4
VSS
A5
A6
A6
A3
A7
A2
A8
A1
6
B1
A1
3
B2
A1
2
B3
A9
B4
A8
B5
A5
B6
A4
B7
A1
B8
A1
7
C1
A1
8
C2
A1
1
C3
A1
0
C4
NC
C5
A7
C6
MCH
C7
A0
C8
DQ
3
D1
DQ
0
D2
A
19/
NC
D3
NC
D4
NC
D5
DQ
31
D6
DQ
30
D7
DQ
29
D8
VCCQ
E1
DQ
4
E2
DQ
2
E3
DQ
1
E4
DQ
27
E5
DQ
28
E6
DQ
26
E7
VCCQ
E8
VSS
F1
DQ
7
F2
DQ
6
F3
DQ
5
F4
RY
/B
Y
#
F5
DQ
25
F6
DQ
24
F7
VSS
F8
VCCQ
G1
DQ
8
G2
DQ
10
G3
DQ
9
G4
DQ
22
G5
DQ
21
G6
DQ
23
G7
VCCQ
G8
DQ
13
H1
DQ
12
H2
DQ
11
H3
WP
#
H4
DQ
17
H5
DQ
19
H6
DQ
18
H7
DQ
20
H8
DQ
15
J1
DQ
14
J2
AD
V#
J3
NC
J4
CE
#
J5
OE
#
J6
IN
D
/W
A
IT
#
J7
DQ
16
J8
VCCQ
K1
RS
T
#
K2
CLK
K3
VSS
K4
VCC
K5
WE
#
K6
NC
K7
MCH
K8
C5
1
1
100N
F
-0603SM
T
C5
1
1
100N
F
-0603SM
T
C51
7
100NF
-0603SM
T
C51
7
100NF
-0603SM
T
J
113
H
EAD
ER
2X1
J
113
H
EAD
ER
2X1
1
1
2
2
SW
9
B3F
-1150
Mo
me
n
ta
ry S
w
it
ch
SW
9
B3F
-1150
Mo
me
n
ta
ry S
w
it
ch
1
3
2
4
C
515
100N
F
-0603SM
T
C
515
100N
F
-0603SM
T
C
510
10N
F
-0603SM
T
C
510
10N
F
-0603SM
T
C
514
10N
F
-0603SM
T
C
514
10N
F
-0603SM
T
R21
8
1K-0603SMT
R21
8
1K-0603SMT
Lattice
FPGA
Loader
LC
M
X
O1200C
-C
SB
G
A
1
3
2
U2
6
Lattice
FPGA
Loader
LC
M
X
O1200C
-C
SB
G
A
1
3
2
U2
6
FP
GA
_
IN
IT
N
A1
NC
A2
NC
A3
FP
GA
_
D
ON
E
A4
FP
GA
_
D
A
T
A
_
1
A5
F
L
ASH
_
AD
D
R
ESS_
1
A6
CLO
C
K
A8
F
L
ASH
_
AD
D
R
ESS_
4
A9
F
L
ASH
_
AD
D
R
ESS_
9
A1
1
F
L
ASH
_
AD
D
R
ESS_
1
9
A1
2
F
L
ASH
_
AD
D
R
ESS_
1
7
A1
3
F
L
ASH
_
AD
D
R
ESS_
1
2
A1
4
NC
B1
FL
A
S
H
_
C
E
_
N
B2
F
L
ASH
_
AD
D
R
ESS_
2
B3
F
L
ASH
_
AD
D
R
ESS_
3
B5
F
L
ASH
_
AD
D
R
ESS_
0
B6
FP
GA
_
D
A
T
A
_
7
B7
F
L
ASH
_
AD
D
R
ESS_
1
3
B8
F
L
ASH
_
AD
D
R
ESS_
5
B9
F
L
ASH
_
AD
D
R
ESS_
7
B1
0
F
L
ASH
_
AD
D
R
ESS_
1
5
B1
2
F
L
ASH
_
AD
D
R
ESS_
1
8
B1
3
F
L
ASH
_
AD
D
R
ESS_
2
1
B1
4
FL
A
S
H
_
OE
_
N
C1
FL
A
S
H
_
D
Q
_
2
2
C2
F
L
A
S
H_CE
0_N
C3
FL
A
S
H
_
D
Q
_
6
C4
FL
A
S
H
_
D
Q
_
2
3
C6
F
L
ASH
_
AD
D
R
ESS_
1
1
C8
F
L
ASH
_
AD
D
R
ESS_
6
C10
F
L
ASH
_
AD
D
R
ESS_
8
C11
F
L
ASH
_
AD
D
R
ESS_
2
0
C12
F
L
ASH
_
AD
D
R
ESS_
1
6
C13
F
L
ASH
_
AD
D
R
ESS_
1
4
C14
FL
A
S
H
_
R
D
/B
Y
D1
FL
A
S
H
_
D
Q
_
7
D3
F
L
A
S
H_DQ
_14
D12
F
L
ASH
_
AD
D
R
ESS_
1
0
D14
F
L
A
S
H_DQ
_16
E2
FP
GA
_
D
A
T
A
_
6
E3
FL
A
S
H
_
D
Q
_
8
E1
3
F
L
A
S
H_DQ
_15
E1
4
F
L
ASH
_
AD
V_
N
F2
F
L
A
S
H_CE
1_N
F3
FL
A
S
H
_
D
Q
_
3
1
F1
2
FL
A
S
H
_
D
Q
_
9
F1
3
FL
A
S
H
_
D
Q
_
1
0
F1
4
FP
GA
_
D
A
T
A
_
0
G1
F
L
A
S
H_DQ
_17
G2
FL
A
S
H
_
D
Q
_
0
G3
FL
A
S
H
_
D
Q
_
1
G1
3
F
L
A
S
H_DQ
_12
G1
4
FL
A
S
H
_
D
Q
_
4
H1
FP
GA
_
P
R
O
GR
A
M
N
H2
FL
A
S
H
_
D
Q
_
2
4
H12
F
L
A
S
H_DQ
_25
H13
F
L
A
S
H_DQ
_30
H14
FL
A
S
H
_
D
Q
_
5
J1
TS
A
L
L
J2
FP
GA
_
D
A
T
A
_
4
J3
F
L
A
S
H_DQ
_13
J1
2
F
L
A
S
H_DQ
_11
J1
3
FP
GA
_
D
A
T
A
_
5
K1
FL
A
S
H
_
W
E
_
N
K2
F
UNC_RE
S
E
T
K1
2
FL
A
S
H
_
D
Q
_
2
K1
3
F
L
A
S
H_DQ
_21
K1
4
FL
A
S
H
_
W
P
_
N
L1
NC
L3
F
L
A
S
H_DQ
_19
L14
NC
M1
NC
M2
NC
M3
NC
M4
NC
M6
NC
M7
FP
GA
_
D
A
T
A
_
3
M8
NC
M9
F
L
A
S
H_DQ
_18
M1
1
NC
M1
2
F
L
A
S
H_DQ
_26
M1
3
F
L
A
S
H_DQ
_27
M1
4
NC
N1
NC
N3
NC
N4
F
L
A
S
H_DQ
_28
N6
NC
N7
NC
N8
FL
A
S
H
_
D
Q
_
3
N9
F
L
A
S
H_DQ
_29
N10
NC
N13
FP
GA
_
R
E
S
E
T
N
N14
NC
P1
FP
GA
_
C
C
L
K
P5
FP
GA
_
D
A
T
A
_
2
P8
NC
P1
0
NC
P1
1
F
L
A
S
H_DQ
_20
P1
2
NC
P1
3
F
L
ASH
_
R
ESET
_
N
P1
4
TC
K
P4
TD
I
M5
TD
O
N5
TM
S
P3
GND
E1
VCC
H3
GND
L2
GND
P2
VCC
P6
VCC
AUX
P7
GND
N11
GND
L13
VCC
G12
GND
D13
GND
A10
VCC
AUX
A7
VCC
C7
GND
B4
GND
F1
GND
P9
GND
J14
GND
C9
VCC
IO
0
C5
VCC
IO
1
B11
VCC
IO
2
E12
VCC
IO
3
L12
VCC
IO
4
M10
VCC
IO
5
N2
VCC
IO
7
D2
VCC
IO
6
K3
SL
EEPN
N12
J1
1
5
JUMP
E
R1
J1
1
5
JUMP
E
R1
1
2
C
516
10N
F
-0603SM
T
C
516
10N
F
-0603SM
T
R
216
4_7K-0603SM
T
R
216
4_7K-0603SM
T