Lattice Semiconductor LFSC80E-P4-EV, User Manual

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LatticeSC PCI Express x4 Evaluation Board
Lattice Semiconductor User’s Guide
PCI Express x1 Cable Connectors
PCI Express x1 Cable Connectors (CON1 and CON2) are provided to demonstrate cable capabilities of the
SERDES channels. These cable connectors conform with the PCI Express Cable Specifications. A simple cable
loopback connected between the connectors can be used to evaluate this feature.
SERDES SMPTE Channels
(see Appendix A, Figure 10)
A single-channel 75-ohm SERDES channel is connected to BNC edge connectors. These connections are pro-
vided to connect to SMPTE video equipment. The channels include the appropriate passive components for
interoperability to SMPTE devices.
Table 8. SERDES SMPTE BNC Connectors (see Appendix A, Figure 10)
J9 A_HDINN1_L
J4 A_HDINP1_L
J21 A_HDOUTN1_L
J14 A_HDOUTP1_L
SERDES PCI Express Channels
(see Appendix A, Figure 10)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1) to fit directly into an x4 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
FPGA Test Pins
General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS
designated according to the following table.
Table 9. FPGA Test Pins (see Appendix A, Figure 7)
Switch BGA Netname LED BGA NetName
SW2D A20 Switch1 D2 A19 RED1
SW2C K22 Switch2 D5 J21 YELLOW1
SW2B K21 Switch3 D7 H21 GREEN1
SW2A G20 Switch4 D9 B18 BLUE1
SW1D F20 Switch5 D3 A18 RED2
SW1C J22 Switch6 D6 H20 YELLOW2
SW1B H22 Switch7 D8 H19 GREEN2
SW1A B19 Switch8 D10 E19 BLUE2
Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be
programmed on FPGA output pins.
J19 B_HDOUTN1_L
J15 B_HDOUTP1_L
J26 B_HDOUTN2_L
J22 B_HDOUTP2_L
J30 B_HDOUTN3_L
J28 B_HDOUTP3_L