Lattice Semiconductor LFSC80E-P4-EV, User Manual

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LatticeSC PCI Express x4 Evaluation Board
Lattice Semiconductor User’s Guide
Table 11. 17-Segment LED Display
Segment BGA
A AC33
B AA30
C AD34
D AA28
E AA33
F AB34
G AA29
H Y31
K Y32
M W24
N W33
P Y34
R W26
S V34
T W25
U U33
DP Y27
A B
C
D
G
F E
DP
H
T S R
K M N
U
P
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit
the evaluation of several FPGA I/O buffer types. The use of several termination schemes permits easy interfaces
for each buffer type.
Table 12. FPGA I/O Test SMA Connectors
SMA
Designation Name LFSC80 Signal
1152
BGA
Termination Description
Termination
Resistor(s)
See Appendix A, Figure 12
J36 LVDS_INP0 PL22A E34 DC-Coupled n/a
J38 LVDS_INN0 PL22B F34 DC-Coupled n/a
J33 LVDS_INP1 PL24A F33 DC-Coupled n/a
J35 LVDS_INN1 PL24B G33 DC-Coupled n/a
J40 LVDS_INP2 PL25A K30 DC-Coupled n/a
J42 LVDS_INN2 PL25B L30 DC-Coupled n/a
J44 LVDS_INP3 PL26A G34 DC-Coupled n/a
J46 LVDS_INN3 PL26B H34 DC-Coupled n/a
J37 LVDS_OUTP0 PL17A F31 100-ohm Differential Termination R114
J32 LVDS_OUTN0 PL17B G31 100-ohm Differential Termination
J34 LVDS_OUTP1 PL18A D33 100-ohm Differential Termination R116
J39 LVDS_OUTN1 PL18B E33 100-ohm Differential Termination
J41 LVDS_OUTP2 PL20A F32 100-ohm Differential Termination R117
J43 LVDS_OUTN2 PL20B G32 100-ohm Differential Termination
J45 LVDS_OUTP3 PL21A H30 100-ohm Differential Termination R118
J47 LVDS_OUTN3 PL21B J30 100-ohm Differential Termination
See Appendix A, Figure 13
J48 URC_PLLT PR16A/URC_PLLC_IN_A F5 50-ohm Ground Termination R166