3
LatticeECP2M PCI Express x4
Lattice Semiconductor
Evaluation Board User’s Guide
Board Features
• SERDES interface to x4 PCI Express edge fingers
• DDR2 memory device
• SERDES high-speed interface SMA test points (active with LatticeECP2M-50 and larger FPGAs only) and clock
connections
• Power connections and power sources
• ispVM
®
programming support
• On-board and external reference clock sources
• Interchangeable clock oscillators
• On-board reference clock management using Lattice ispClock™ devices
– ORCAstra demonstration software interface via standard ispVM JTAG connection
– Various high-speed layout structures
• User defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 1 shows the functional partitioning of the board.
Figure 2. LatticeECP2M PCI Express x4 Evaluation Board
LatticeECP2Mxx
672 fpBGA
isp
V
M/JTAG
8
L
V
DS Paired SMAs for
Demo of L
V
DS I/O
Performance
BNC Connector
DDR2
Memory
Component
General P
u
rpose
I/Os -
S
w
itches/LEDs
SMAs for a Single
1 Q
u
ad of 3G
(SRIO x1, x4),
XAUI
4 SMAs for External
Clock So
u
rces
Oscillators
PCI Express (x4)
Edge Fingers
FPGA Loader
SPI Flash De
v
ice
