Lattice Semiconductor LatticeECP2M PCI Express x4, User Manual

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Test Pad Array
A 5 x 12 array of test pads are provided for the user to utilize for test points. This array provides 48 general I/O con-
tacts and 12 ground points.
Table 9. Test Pad Array BGA Reference
High Speed Test Point
(see Appendix A, Figure 13)
DP1
General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
(see Appendix A, Figure 14)
U18
The LatticeECP2M Evaluation Board is equipped to an 84-ball BGA DDR2 SDRAM memory device such as a
Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation
board includes termination of address and command signals. It includes all power and external components
needed to demonstrate the memory controller of the LatticeECP2M device
J44 LVDS_OUT N 1 PR53B V25
J46 LVDS_OUTP2 PR55A W26 100-ohm Differential R135
J48 LVDS_OUT N 2 PR55B W25
J50 LVDS_OUTP3 PR59A Y26 100-ohm Differential R137
J52 LVDS_OUT N 3 PR59A AA26
AA20 V17 W20 AC25 AC23 AD26 AB21 AC22 AD12 AF12 W14 AB13
AA13 AE9 AF9 AB6 E23 E24 P26 P25 U21 U19 V21 J2
GND GND GND GND GND GND GND GND GND GND GND GND
K7 J6 K5 L5 P5 N 6 P4 R3 W5 Y4 U8 W6
G7 G8 E6 D5 G12 C8 E13 H17 E14 G17 D17 E17
Table 8. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13) (Continued)
SMA
Designation Name
LFE2M35E
Signal 672-BGA
Termination
Description
Termination
Resistor(s)
1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16 17 1 8 19 20 21 22 23 24
25 26 27 2 8 29 30 31 32 33 34 35 36
37 3 8 39 40 41 42 43 44 45 46 47 4 8
49 50 51 52 53 54 55 56 57 5 8 59 60
Test Points Array on Component Side